App note: Terminations for advanced CMOS logic

App note from ON semiconductor on proper terminations when using advance CMOS logic to minimize power consumption. Link here (PDF)

Advanced CMOS logic such as ON Semiconductor’s FACT® logic, has extended CMOS performance to the level of advanced bipolar technologies. While high−performance design rules that are currently utilized for bipolar designs are also applicable to CMOS, power consumption becomes a new area of concern in high−performance system designs.
One advantage of using advanced CMOS logic is its low power consumption. However careless circuit design can increase power consumption, possibly by several orders of magnitude. A simple FACT gate typically consumes 625 W/MHz of power; at 10 MHz, this translates to 6.25 mW. A 50 W parallel termination on the line will use over 361 mW with a 50% duty cycle.

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