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App note: Analyzing VIN overstress in power ICs

Posted on Sunday, September 9th, 2018 in app notes by DP

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Investigative app note from Richtek about the component failure point caused by EOS. Link here (PDF)

Failures in power ICs are often the result of Electrical Over Stress (EOS) on the IC input supply pin. This report explains the structure of power IC input ESD protection and how ESD cells can become damaged due to EOS. Common causes for input EOS are hot-plug events and other transient effects involving wire or trace inductance in combination with low ESR ceramic capacitors. Solutions are presented how to avoid EOS via special circuit and system design considerations.

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