Xilinx application note (PDF!) on MMCM and PLL dynamic reconfiguration:
This application note describes the information necessary to reconfigure the MMCM or PLL and provides a reference design that implements all of the algorithms covered. The PLL and MMCM share very similar functionality but are not identical. Due to some subtle functionality differences and the requirement for different settings, a separate PLL reference design is provided. To ensure correct operation, use the correct reference design for the clock management tile (CMT) being reconfigured.
Reconfiguration is performed through the DRP. The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM or PLL clock outputs while the design is running. Frequency, phase, and duty cycle can all be changed dynamically. Fine-phase shifting is not allowed for the initial configuration or during reconfiguration.