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Hacking footprints for easier 2 layer routing

Posted on Friday, January 4th, 2013 in hacks, PCBs by DP

SpecialTSSOP

Routing complex surface mount circuits on a 1 or 2 layer PCB is tricky. TSSOP and similar small parts often don’t have enough clearance to route a trace between two leads. Mats tackled this by by removing a few unused leads. This gave him the freedom to route traces through the now available space where the pins used to be. This is certainly never something to do on a production board, but it might save the day for 1 and 2 layer hobby PCBs, especially homemade PCBs.

Here I didn’t need the Q3 and Q4 outputs on a latch so I shrunk down the size of the pads to minimum size and then removed the stop mask on them so they are covered. This makes it easy for me to route a wire between the other pads – something that can’t be done on a TSSOP package since the pads are too close together to fit a normal wire between them.

Via the forum.

This entry was posted on Friday, January 4th, 2013 at 11:00 am and is filed under hacks, PCBs. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

6 Responses to “Hacking footprints for easier 2 layer routing”

  1. That works quite nicely if cut of the unsued pins of the chip with a wire cutter.

  2. Very neat trick. I remember doing something similar with a DIP8 device (dunno why, since there’s plenty room to rout a track between pads, but anyway).

    Somebody mentioned (maybe it was on here) that it’s sometimes possible to rout traces through an existing pin, if it’s set to an input. E.g. say you had an output from a micro – just rout it through an un-needed pin that’s configured as an input.

  3. vimark says:

    very clever

  4. Asm says:

    Actually, this happens on production boards too (well, used to anyway). It’s often common to slap some silkscreen over the traces at the point where they intersect with the now unsoldered pins, just in case the soldermask has flaws.

    There is really nothing wrong with doing this apart from looking a bit silly.

  5. JesseJ says:

    Simply dropping two bits into the mix here. Unused CPLD and FPGA pins tend to default as inputs in
    the compile flow. Will still present a small amount of loading to the trace, but otherwise should be okay.

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