NEW PROTOTYPE: CoolRunner-II CPLD development board

Ever get stuck choosing the right logic chip combination or voltage level translator? Give up the hunt and create your own custom logic chip. CPLDs can give you the logic you need, with the pinout you want, while saving board space and board revisions.

The CoolRunner-II XC2C CPLD has two separate banks of pins that can operate at different voltages, internal pull-up resistors, and pin keepers.  This development board will help you build your first custom logic chip using simple schematic entry, Verilog, or VHDL.

We’re really excited to see what you do with these boards. Adding this CPLD to the Bus Blaster v2 JTAG programmer turned it into a crazy morphing muti-programmer clone.

Hardware design overview

  • XC2C64A CPLD with 64 macrocells
  • On-board 1.8volt supply for the core
  • On-board 3.3volt supply for pins
  • Separate pin banks can be operated at different voltages (1.2volt to 3.3volt)
  • Selectable 1.8volt, 3.3volt, and external supply for each pin bank
  • LEDs for output
  • Push button for input
  • Populated JTAG header
  • Unpopulated oscillator footprint on the bottom
  • Pre-programmed with LED inverse toggle demo
  • Easy to program with the Bus Pirate and Bus Blaster
  • Open source (CC-BY-SA)


We’ve been interested in CPLDs and FPGAs for a few months now, and there’s already several CPLD resources on the wiki:

You can get the CoolRunner-II development board for $15. A XC9572XL dev-board is also available for $15.

Have an idea for this dev-board? Share it in the comments and we’ll send you the PCB (while they last).

Join the Conversation


  1. Noob question. Why would I chose one of the other dev boards? I guess for $15 I could go for both, but hey I like to be in one camp and stay there :)

    1. PS I’ve read the comparison page above now – I’m assuming then that the Coolrunner is the more preferable target, since the XC9572XL is part of the XC9500 family and gets tarred with that brush?

      1. It really depends on the app. XC9500XL is the cheapest CPLDs I know of (that is readily available and solder-able by a mere human). It is faster than the CoolRunner-II, has 5volt tolerant inputs, and can run from a single 3.3volt power supply.

        The CoolRunnerII is newer, slightly more expensive, but slightly slower with lower power use. has some perks like pull-up resistors and multiple voltage banks, but requires a 1.8volt core supply.

        My take: if you need 5volt tolerant pins in a 3.3volt environment it will probably be cheapest to use the XC9500XL. If you need translation between nodes at 3.3volts-1.2volts (like the Bus Blaster v2 interface) use the CoolRunner-II. For general purpose use, the chips are almost interchangeable (obviously depends on the app).

      2. I just wanted to add – I use the XC9500XL whenever possible, it is my ‘favorite’ because it is 5volt tolerant, cheap, and only needs one supply. However, the pull-ups on the CoolRunner-II are really attractive, and can really rescue a design from a poorly planned PCB with a simple update.

      3. > It is faster than the CoolRunner-II…

        Isn’t that backwards? Looking at the photos I see the proto boards are stuffed with the XC9572XL in the -10 speed grade (10 ns delay) whereas the XC2C64A (coolrunner II) board is sporting a -7 speed grade (7 ns). Referring to the data sheets, I see Fsystem = 159 / 141 MHz for the CoolRunner II (-7 speed) but Fsystem = 100 MHz for XC9572XL-10. (on page 6) (on page 4)

      4. You are correct about this chip, but I meant overall, the XC9500XL family has a greater maximum speed than the CoolRunner-II. I could also be wrong about that though :)

  2. Here is my idea: I would take several ADCs, hook them all up to the CPLD and serialize the voltage data to send it over one line (clock, data and reset).
    On the other side, I would place another CPLD to deserialize the bit stream and feed it into several DACs. Add a buffer at the input and an amp at the output and tata! you have analog data transmission over long distances with decreased noise along the way!

  3. My idea is to make a CPLD version of a TIC (Time Interval Counter), specifically the PICTIC II as shown here:

    As you see from the schematic, this circuit uses several 74AC logic packages (Dual D FF 74AC74, Quad D FF 74AC175, 4-bit counter 74AC163 all of which fits easily into the CPLD, with room to spare for a 16-bit up counter. (Note the 74AC175 is not even available anymore, at least in the DIP package.) Using a simple 2N3906 current source steered by external diodes into a 1000 pf integrating capacitor, and an A/D, the PICTIC circuit interpolates the delay in-between clock edge and input signal edge to achieve sub-nanosecond timing resolution.

    It’s always better to have a high basic clock rate in a TIC for best resolution, to reduce the analog interpolation interval which is always affected by temperature & voltage drift. So I want to run the CPLD at the highest reliable clock speed… I guess I’ll find out what that is.

Leave a comment

Your email address will not be published. Required fields are marked *

Notify me of followup comments via e-mail. You can also subscribe without commenting.