Xilinx CPLDs: XC9500 vs CoolRunner-II
The two cheapest and most readily available Xilinx CPLD families are the XC9500XL and CoolRunner-II. Both are in stock at Digikey in a variety of packages. We wondered what exactly the differences are, here's our notes in a table.
|Cost||Cheapest (from $1.07 for the 36 macrocell XC9536XL)||Cheap (from $1.25 for the 32 macrocell XC2C32A)|
|Core supply||XC9500XL is 3.3volt. Older expensive XC9500- is 5volt||1.8volt|
|IO supply||9500XL is 2.5 or 3.3V IO, 9500- is 2.5V, 3.3V, or 5V IO||1.5-3.3volt IO|
|5volt tolerant pins||All pins 5volt tolerant||Only expensive XPLA3 portable version|
|Voltage translation||All pins run at the same voltage||2 or more banks with independent supplies|
|Power use||Higher power, slightly faster||CMOS technology, lower power|
|Flash endurance||10,000 write cycles||1,000 write cycles|
|Goodies||GCK, GTS, GSR||clock divider, clock multiplier, multiple IO banks, GCK, GTS, GSR|
Our take away is below.
- Use CoolRunner-II whenever possible
- More modern
- Lower power
- Multiple IO voltage banks
The CoolRunner-II is newer, slightly more expensive, but slightly slower with lower power use. Has some perks like pull-up resistors and multiple voltage banks, but requires a 1.8volt core supply. Note the 1,000 limit for flash memory write cycles.
- Use XC9500XL if you need 5volt tolerance
- Forget the older XC9500 5volt parts, they're dead
- Might be good for huge quantity projects where a few cents matters
- Probably still around for legacy designs
XC9500XL is the cheaper CPLD. It is faster than the CoolRunner-II, has 5volt tolerant inputs, and can run from a single 3.3volt power supply. Note the 10,000 limit for flash memory write cycles.
If you need 5volt tolerant pins in a 3.3volt environment it will probably be cheapest to use the XC9500XL. If you need translation between nodes at 3.3volts-1.2volts (like the Bus Blaster v2 interface) use the CoolRunner-II. For general purpose use, the chips are almost interchangeable (obviously depends on the app).
There are also some pins with special features, though they are not used unless specifically enabled in the CPLD synthesis:
- GCK (global clock) - optimized to distribute a clock signal to all macrocells with minimum skew and extra resources
- GSR (global set reset) - optimized path to the Set/Reset signal of all macrocells, allows synchronous reset of the flip-flop in all cells with minimum extra resources
- GTS (global tri-state) - optimized to put all CPLD pins in a high impedance state