All new Logic Sniffer FPGA core

dogsbody rewrote the entire Logic Sniffer FPGA core in Verilog and added nearly all the features of a HP 16550A workbench logic analyzer. Check it out:

My version of the fpga uses 85% of the slices, keeps the legacy triggers, meets timing easily (at 105Mhz), and adds:

Trigger Terms:
10 more 32-bit masked value comparisons.
2 range checks.
2 edge checks (rising, falling, both, neither).
2 36-bit timers (10ns to 600sec range).

States:
16 state FSM
Each state can use any combination (AND/NAND/OR/NOR/XOR/NXOR) of the trigger terms for detecting a “hit” condition, and “else” condition, or “capture” condition.

Each state also has a 20-bit hit count that must be reached before a full “hit” occurs. Hit actions include setting trigger(run),
starting/stopping timers, and advancing to the next state.

The “else” condition lets you punt to another state.

The “capture” condition lets you control what gets sampled into RAM, until you flip the trigger.

…Grab the 16550a user’s guide. I think you’ll be surprised how much got squeezed in.

Get a Logic Sniffer for $50, with free worldwide shipping.

Via the forum.