App note: Implementation of error code correction in EEPROMs

App note from ON Semiconductors about their EEPROM error correction. Link here (PDF)

Some of ON’s automotive EEPROMs, like the Grade 0 NV25xxx family (SPI, 1 – 64 Kb) and the Grade 1 CAV24Cxx / CAV25xxx (Grade 1, 128 Kb and higher) implement an Error Code Correction scheme. What this means is that for each chunk of data in the EEPROM array (8 bits for 1 – 64 Kb densities, 32 bits for 128 Kb and higher), the memory stores a redundancy code in separate EEPROM cells.

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