App note from Infineon about quad SPI, an enhanced SPI protocol that provides four times data throughput at higher frequencies. Link here (PDF)
In order to manage the wide range of multimedia, graphics, and other data intensive content, embedded systems have evolved to offer more sophisticated features. These features place extra demands on the often-limited on-chip memory of the host controller (or MCU). External memories with parallel interface have long been used to extend the on-chip MCU’s storage limitations. Memories with a parallel address/data bus come in high pin-count packages and require more pins on the controller to communicate with.
The QSPI F-RAM supports single data rate (SDR) for all its SPI interface options up to 108 MHz, while it also supports the double data rate (DDR) up to 54 MHz but for specific opcodes. The 54-MHz DDR interface offers the same data throughput as the 108-MHz SDR but at half the frequency. Some systems preferably use DDR at reduced frequency than the high-speed SDR, which helps reducing the system core and I/O frequencies, thus system power without compromising the data throughput.