App note from ON Semiconductors that discuss tradeoffs between achivieng low quiescent current and good dynamic performance when choosing an LDO. Link here (PDF)
One of the most important challenges today in designing electronic applications is to minimize the power consumption of the system. To accomplish this, most systems utilize various low power modes which help to minimize the overall power consumption. When utilizing various modes of operation, system supply currents can easily vary from single A or even fractions of A in sleep to tenths or hundreds of mA in full power mode. Low Dropout Linear Voltage Regulators (popularly referred to as LDOs) are common building blocks in any power system and the choice of linear regulator can have an important impact on the overall system power consumption. To complicate this choice, it is often required that the LDO not only feature ultra−low quiescent current but should additionally provide good dynamic performance to assure stable, noise−free voltage rail, suitable for sensitive circuits.