App note from Abracon about problems due on large crystal capacitive loading on smaller sized MCUs. Link here (PDF)
The 18pF plated Quartz Crystals may no longer be the ideal choice for a typical clocking circuit using an off-the- shelf MCU. As silicon geometries have shrunk over the last decade, the Pierce oscillator loop embedded in typical MCU’s has also evolved.
The latest 22nm, 14nm and now 10nm silicon geometries are bringing many benefits such as decrease in total IC size & reduction in power consumption – while incorporating feature rich capabilities. However, these advancements present challenges in the typical Pierce oscillator loop for system engineers.
In particular, these advancements in silicon geometry have decreased amplifier/inverter’s transconductance, gm , in the crystal oscillator loop. The results are power starved oscillation circuits that are marginally functional. These circuits run the risk of failing to startup due to total capacitive loading, changes in temperature & bias levels, etc.