Open source RISC – Eclipse with RISC-V on the SiFive HiFive1 board

Posted on Friday, August 17th, 2018 in open source by DP


Erich Styger writes:

Open Source software has been around for decades. But open source on hardware especially microcontroller is not much a reality these days. But there is something which might change this: RISC-V is a free and open RISC instruction set architecture and for me it has the potential to replace some of the proprietary architectures currently used. RISC-V is not new, but it gets more and more traction in Academia (no surprise). Not only because it is open: Think about all the recent security issues with proprietary architectures: Spectre, Meltdown, and Foreshadow just be the most recent one.
I wanted to play with RISC-V for over a year, but finally a week ago I did one of these “hey, let’s buy that board” thing again. Sometimes these boards get on a pile to wait a few weeks or longer to get used, but that one I had to try out immediately :-).

More details on MCU on Eclipse site.

This entry was posted on Friday, August 17th, 2018 at 11:40 pm and is filed under open source. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

One Response to “Open source RISC – Eclipse with RISC-V on the SiFive HiFive1 board”

  1. KH says:

    I didn’t like parts of his article. He perhaps thinks an open source microarch can help prevent potential security issues, and ties it to Spectre, Meltdown, etc. IMHO it’s a stupid claim, because academia had also been playing with the same microarchs as commercial CPUs for years. Everyone was mostly focused on performance, not security. So everyone screwed up, let’s not be naive and assume open source hardware will be somehow better — how many people will download a hardware design and audit the thing thoroughly? And who did that for the SPARC open-sourced stuff? Maybe just the NSA, GRU, Mossad and similar orgs. Most people just fiddled and compiled and ran the SPARC designs on FPGAs; who checked anything in detail eh?

    The MCU part on HiFive1 is very unbalanced, consider it just an engineering prototype thing. 320MHz capable CPU but only 16KB SRAM, ha ha. HiFive Unleashed is better, but it’s an expensive board. Until something with a better balanced feature and cost mix comes along, I would rather play with RISC-V on QEMU. No matter that they say about open this or that, you still need to get the parts fabbed in an IC foundry. So I might as well keep to MCHP/ATML.

    A more interesting development is that WD and Nvidia are using RISC-V seriously. But where cost-size-efficiency is really really important, RISC-V will probably not be better than the really lean and mean stuff for deeply embedded stuff like ARC or nanoMIPS.

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