App note (PDF) from KEMET on different decoupling capacitors for each board power line requirements.
Integrated circuit (IC) technology has advanced over time, requiring innovative decoupling solutions that address decoupling needs over the entire power path from the main power supply to the logic gates on the IC. As one follows the path from the power supply to logic gate, high-frequency content increases, required capacitance falls, and the importance of very low inductance (ESL) increases. Impedance (Z) must also remain low and stable over the frequency range of interest so that detrimental resonances are avoided. Four tiers or levels of decoupling have been defined along the path from the power supply to the logic gates on the IC: (1) the voltage regulator level, (2) the board decoupling level, (3) the IC package decoupling level, and (4) the IC on-die decoupling level. Each level has impedance requirements that are best addressed by capacitor technologies which differ in capacitance density, capacitance stability, ESL, ESR and cost.
This paper addresses the relative performance of competing capacitor technologies for board level (2) and IC package level (3) decoupling. New decoupling paradigms are presented for both of these levels.