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App note: Understanding and Minimizing Ground Bounce

Posted on Sunday, May 11th, 2014 in app notes by DP

FC_AN640

Another old app note from Fairchild on Ground Bounce issues.

Ground bounce has been a concern to some system designers for many years. Its effects can be found in most bipolar and CMOS logic families. However, ground bounce has recently become a major issue. Although new advanced CMOS logic families have edge rates comparable to advanced bipolar logic devices, CMOS outputs swing almost from rail to rail while bipolar outputs swing from ground to approximately 3.0V. These edge rates, coupled with the greater voltage swings found in today’s advanced CMOS logic devices, tend to generate more ground bounce noise than their bipolar counterparts.

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5 Responses to “App note: Understanding and Minimizing Ground Bounce”

  1. Drone says:

    “Another old app note from Fairchild on Ground Bounce issues.”

    In this post, does this “Another” refer to two app note links? I see only one reference to the “old app from Fairchild” (which is classic). If I’m wrong, provide the link to the “other” app note. Otherwise, refrain from using the work Another (which implies more than one) in your description.

    No I’m not the “English Police”. But this one seems glaring.

  2. MrCircuitMatt says:

    Most likely, they are referring to their other post they made earlier that day: http://dangerousprototypes.com/2014/05/11/app-note-using-fairchilds-lvx-low-voltage-dual-supply-cmos-translating-transceivers/

    So the first app note would be an old app note from Fairchild on their voltage translating devices, and the one on ground bounce is ‘another old app note from Fairchild’. Honestly I don’t see any problem here…

    Regards
    Matt

  3. Evan says:

    It is reference to the previous post “An fairly old app note on fairchilds take on voltage translation ICs”

    • vimark says:

      Thanks Evan, It was indeed in reference to the earlier post from the same manufacturer “Fairchild”

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