Very happy to report that my first try at a Coolrunner II CPLD project works! This is the 16-bit timer with start / stop pulse inputs. It is only tested so far up to 4 MHz, using the Bus Pirate as a signal generator (and also doubling as a JTAG programmer- handy tool!). The timing report claims it can go a bit further :-). Thanks DP for the help and the nice CPLD board!
Download the schematic, pinout, simulation, and XSVF files in the forum.