The large CPLD schematic library guide posted yesterday contains a lot of reference material to digest. You may be wondering just how to get started with writing program files using the Xilinx ISE WebPACK software package. We found this concise tutorial by Digilent, Inc. covering the basics of creating a CPLD program using the schematic entry method.
Note that this tutorial was written for use with a Digilent Nexys2 FPGA dev board. The differences to note when using our CPLD dev boards are on the New Project Wizard/Device Properties Screen, where you are asked to specify the Device Family, Device and Package. For the XC9572XL board, the Device Family is XC9500XL CPLDs, the Device is XC9572XL and the Package is VQ44; for the CoolRunner-II board, the Device Family is CoolRunner2 CPLDs, Device is XC2C64A and Package is VQ44. Also, for CPLDs you will not need to set the Startup Clock options on page 15 of the tutorial.
A very useful guide, and quite timely given the CPLD boards’ arrival- thanks!
I did the experiment several years ago of creating the same design in WebPack as both a schematic, and Verilog source file. In terms of overall effort required, the Verilog version was much easier.
When you’re working with a schematic, moving or changing things is actually a lot of work, because you have to edit the drawing in such a way that the graphics still read well. This is a lot more time consuming than just changing a line or two of text.
The experiment convinced me it’s worth the effort to learn one of the two languages (VHDL/Verilog) if you’re going to be doing gate array work. Fortunately, there’s a lot of good tutorial material on the web.
Interesting aside: The schematic editor in WebPack (at least at the time I was using it) worked by taking the drawing’s netlist and converting it to a VHDL or Verilog source file for subsequent processing.