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Bus Pirate extended logic analyzer firmware

Posted on Thursday, March 31st, 2011 in Bus Pirate, firmware by Ian

flubberlab made an alternate firmware for the Bus Pirate with extended support for the SUMP logic analyzer protocol. This firmware works with the latest Jawi client and has lots of features:

Sample clock source (32 MHz CPU clock):

  • Internal, 5.9 Hz to 108.8 kHz, jitter = -0/+250 ns
  • External (via AUX pin), rising or falling, 0 Hz to 100.6 kHz, jitter = -0/+563 ns (falling), -0/+625ns (rising)

Trigger:

  • Parallel only
  • Conforms to SUMP basic trigger system (4 sum terms, each with mask/value/delay/level/action)
  • Stages are evaluated sequentially, i.e. 1-2-3-4, on each sample

Other

  • Sample buffer is pre-filled with telltale data (0,1,2…255,0,1…) to help indicate when a trigger occurs before the pre-trigger buffer is filled.
  • OLS internal test mode supported (data = 0,1,2…255,0,1…)

Firmware is available in the forum, load it with the normal Bus Pirate upgrade method.

Get your own handy Bus Pirate for $30, including world-wide shipping. Also available from our friendly distributors.

This entry was posted on Thursday, March 31st, 2011 at 10:03 pm and is filed under Bus Pirate, firmware. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

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