Bus Blaster v2: JTAG Serial Wire Debug support

Posted on Wednesday, March 16th, 2011 in Bus Blaster, JTAG by Ian

A KT-link buffer clone supporting JTAG Serial Wire Debug is now available for Bus Blaster v2 pre-release testers. This should support the new 2-wire SWD debugging protocol when available in OpenOCD and urJTAG.

The KT-link is the first FT2232-based JTAG debugger with support for the new SWD and SWV JTAG interface used on low pin count ARM chips. The libswd project is adding support for SWD to OpenOCD and urJTAG, and the KT-link will be the first supported programmer.

Bus Blaster v2 is buffered by a reprogrammable CPLD instead of discrete logic chips. New buffer logic can be loaded so the Bus Blaster appears like many common JTAG debuggers. In anticipation of the Bus Blaster v2 release, we prepared this KT-link compatible buffer clone that can be loaded into the CPLD. See all the Bus Blaster v2 buffers. Join development discussion in the forum.

This entry was posted on Wednesday, March 16th, 2011 at 11:57 am and is filed under Bus Blaster, JTAG. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

7 Responses to “Bus Blaster v2: JTAG Serial Wire Debug support”

  1. Nikos says:

    Is it possible to mod the bus blaster cpld to support SWV ?

  2. ian says:

    Because of the way the cpld is programmed by the second Jtag port it is not. We built a v4 that can do this though.

  3. mohammad says:

    Can we use it for programming qualcomm microprocessors
    like msm7227.

  4. Ian says:

    Support depends on the software. If openocd supports it or the manufacturers software supports jtagkey or ktlink processors then it could work.

  5. Can programming boards via JTAG be done using the BusPirate instead? I don’t understand the difference between the Pirate and Blaster

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