Bus Blaster v2 development

Posted on Sunday, December 19th, 2010 in Bus Blaster, Development by Ian

We got a big box of PCBs from Seeed this week. This is an update of the Bus Blaster (in test production now) with a CPLD instead of discrete logic buffer chips.

The CPLD is connected to the secondary JTAG B port of the ft2232. This should make it like a mini CPLD development board, as well as a JTAG debugging tool.

We currently have a bit of an issue because most popular JTAG apps, like URJTAG, only support the ft2232’s JTAG A port. If you have any ideas, or would like to be involved in development or testing, please join us in the forum.

This entry was posted on Sunday, December 19th, 2010 at 9:54 am and is filed under Bus Blaster, Development. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

4 Responses to “Bus Blaster v2 development”

  1. FoXCoRe says:

    I’d be glad to have one !

  2. tomi says:

    one for me

  3. Ian says:

    Sorry guys
    , this wasn’t the Greeley Sunday this week :)

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