Claire: Bus Blaster v2

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Claire: Bus Blaster v2
Codename Claire
Status Software
Development development forum
ID # {{{id}}}

This is the early development work on Bus Blaster v2. This page is outdated!!

An update of the Bus Blaster with a CPLD instead of discrete logic buffer chips.

Contents

Prototypes

Bus-blaster-v2.jpg

Busblaster-v2-prototype1.jpgBusblaster-v2-debug-.jpgBusblaster-v2.jpg

Schematic

Busblaster-v2-cctii.png

Busblaster-v2-cct.png

PCB

BusBlaster-v2-pcb.png Busblaster-v2-brd.png

Partslist

partlist
Parts Quantity Value Package
C1-C7, C13-C21 16 100nF C805
C11-C12, C22 3 4.7uF SMC_A
C8 1 3.3uF SMC_A
C9,C10 1 27pF C805
IC1 1 FT2232H LQFP64
IC2 1 93C46 SOIC8
IC3 1 LD1117-3.3 SOT223
IC9 1 XC2C32A_VQ44_2 VQ44
JP1 1X06
JP2 1X09
JP3 1X05
JP4 1X02
JTAG 1 PINHEAD_-_COPY_PINSHRD_PTH_2X10
L1,L2 2 FB805
PWR,TGT 2 CHIPLED_0805
R1 1 12K R805
R10,R11 2 470 R805
R2,R9 2 1K R805
R3-R5, R7 4 10K R805
R6 1 2.2K R805
R8 1 100k R805
T1 1 SOT23-BEC
USB 1 CONN_USB CONN_USB_MINI-B
X1 1 CRYSTAL_212M_ 4X6

Patch apps to see the CPLD

CPLD implementation

Bbv2-jtagkey-cpld-v11.png

Busblaster-v2-cpld-design.png

CPLD synthesis report

Summary

Design Name BBv2JTAGKEY
Fitting Status Successful
Software Version M.53d
Device Used [# XC2C32A-4-VQ44]
Date 1-22-2011, 8:09AM
RESOURCES SUMMARY
Macrocells Used Pterms Used Registers Used Pins Used Function Block Inputs Used
11/32 (35%) 14/112 (13%) 0/32 (0%) 24/33 (73%) 14/80 (18%)
PIN RESOURCES
Signal Type Required Mapped
Input 13 13
Output 10 10
Bidirectional 1 1
GCK 0 0
GTS 0 0
GSR 0 0


Pin Type Used Total
I 1 1
I/O 15 25
GCK/IO 3 3
GTS/IO 4 4
GSR/IO 1 1
DGE/IO 0 -1

Programming the CPLD with urJTAG

Bus Blaster v2 can program the CPLD itself using our patched version of urJTAG. Hopefully our patches will be included in an official release soon.

Setup

Download and install the drivers:

Download and install urJTAG:

Download the CPLD implementation:

Patched urJTAG

We patched urJTAG to allow the Bus Blaster v2 to self-program. Follow these steps to setup:

  1. Download and install UrJTAG
  2. Copy the patched .exe file (urjtag-revXX.exe) to the install location (C:\Program Files\UrJTAG)
  3. Copy \bsdl and \svf to c:\, or see the notes section below.

Program

Patched-urjtag-full-program-bbv2-v1.png

In this step we load the CPLD with the buffer logic.

First, start the patched urJTAG by running the patched exe file (urjtag-revXX.exe) and connect Bus Blaster v2 USB to a computer.

jtag> cable ft2232 interface=1
Connected to libftd2xx driver.
jtag>

Select the Bus Blaster programmer.

jtag> bsdl path c:/bsdl
jtag>

Copy the xc2c32a bdsl file to a directory and tell urJTAG where to find it.

jtag> detect
IR length: 8
Chain length: 1
Device Id: 00000110111000011100000010010011 (0x06E1C093)
Filename:     c:/bsdl/xc2c32a_vq44.bsd
jtag>

Enumerate the devices.

jtag> svf c:/svf/bbv2.svf progress stop
Parsing    660/663 ( 99%)
Scanned device output matched expected TDO values.
jtag>

Copy the .SVF file to a directory. Run the Bus Blaster v2 SVF file. Show progress, stop on errors.

For multiple units:

  1. Press the up arrow once to display the last svf command
  2. Press enter to repeat the final step

Notes

Bus-blaster-v2-block-diagra.png

  • The cable type for the self-program connection is FT2232, option interface=1 targets the CPLD
  • Our patched version of urJTAG requires path names with / instead of \
  • Copy the bsdl file to c:\bsdl, or change the location in the bsdl path command
  • Copy the bbv2.svf file to c:\svf, or change the path in the svf command

NEW TEST with self test buffer

OLD TEST with real JTAG target

Connections

Bbv2-manufacturing-test-ols.jpg

We will chain scan the FPGA on the Logic Sniffer to verify the Bus Blaster functionality. You can use any simple FPGA, CPLD, or ARM development board for the test instead.

test connections
Bus Blaster JTAG Logic Sniffer JTAG
VTG 2V5
GND GND
TCK TCK
TDO TDO
TDI TDI
TMS TMS
  1. Connect the Bus Blaster to the Logic Sniffer as shown in the table
  2. Plug in the Bus Blaster USB
  3. Plug in the Logic Sniffer USB

Function test

Urjtag-bbv1-test-full.png

  • Start urJTAG
jtag> cable jtagkey
  • Setup the Bus Blaster interface with "cable jtagkey"
jtag> detect
  • Perform the chain scan with "detect"
  • urJTAG detects a Xilinx device, manufacturer unknown

Errors

jtag> detect
Warning: TDO seems to be stuck at 1

If the chip is not detected:

  • Check the JTAG connection
  • Make sure there are no other FTDI chips attached to the PC (urJTAG might attach to wrong programmer)

Old program method using Bus Blaster v1

Busblaster-v2-debug-manu.jpg

Connections

We used urJTAG and Bus Blaster v1 to program the CPLD in Bus Blaster v2. Hopefully Bus Blaster v2 will be able to program the CPLD itself, but urJTAG doesn't yet support the secondary JTAG channel on the FT2232.

programming connections
Bus Blaster V1 JTAG Bus Blaster v2 JP1
VTG 3V3
GND GND
TCK TCK
TDO TDO
TDI TDI
TMS TMS
  1. Plug in the Bus Blaster v1 USB to the programming computer
  2. Plug in the Bus Blaster v2 USB to a DIFFERENT computer (so the driver is not confused)
  3. Connect the Bus Blaster v1 JTAG header to the Bus Blaster v2 JP1 as shown in the table

Program

Bbv1-full-program-bbv2.png

In this step we load the CPLD with the buffer logic.

jtag> cable jtagkey

Select the Bus Blaster programmer.

jtag> bsdl path c:\bsdl

Copy the xc2c32a.bdsl file to a directory and tell urJTAG where to find it.

jtag> detect

Enumerate the devices.

jtag> svf c:\svf\bbv2.svf progress stop

Copy the .SVF file to a directory. Run the Bus Blaster v2 SVF file. Show progress, stop on errors.

For multiple units, just repeat the final step.


CPLD tests

Busblaster-v2-hello-world.png

Busblasterv2-cpld-detectedbybbv1.png

Conceptual drawings

Busblaster-v2-diagram.png


BusBlaster-v2-sketch-.png Bus Blaster-con-.jpg

Resources