We’d like your feedback on a major change to the Bus Pirate firmware. We’d like to restore the pin order to the more logical format found on the va and v1a hardware.
The original pin order for va and v1a hardware was MOSI/CLOCK/MISO/CS on single row of pin headers. Pin 1 (MOSI) is the most often used pin, required for all protocols. Pin 2 adds clock, pin 3 adds dedicated data input, and pin 4 adds chip select. See the protocol pinout table above.
The current pin order on v2go and v3 hardware, as seen on a ribbon cable, is MISO/CS/MOSI/CLOCK. This is a lot less intuitive. When we routed the v2go PCBs with a 2×5 pin header, we didn’t pay attention to the change in signal order until it was too late.
We’ve considered changing it several times, but a few things have stopped us. It will be a fairly involved undertaking to update the firmware and test all the protocols. But the primary reason is that existing Bus Pirate v2go and v3 pinouts won’t match the silk screen on the back.
What do you think? Is it worth the effort and ensuing confusion when the pinout changes?