Scott from SWHarden has published a new build:
Today I made a high frequency multiplier using a single component: the ICS501 PLL clock multiplier IC. This chip provides 2x, 5x, 8x (and more) clock multiplication using an internal phased-lock loop (PLL). At less than a dollar on eBay, $1.55 on mouser, and $0.67 on Digikey, they don’t break the bank and I’m glad I have a few in my junk box! I have a 10MHz frequency standard which I want to use to measure some 1Hz (1pps) pulses with higher precision, so my general idea is to use a frequency multiplier circuit to increase the frequency (to 80 MHz) and use this to run a counter IC to measure the number of clock pulses between the PPS pulses.
More details at SWHarden homepage.
For low frequencies, just measure the period and then take the reciprocal. f = 1/p
Much faster and simpler :)
IDT’s ICS5xx series is venerable – and useful if you are careful about what you are trying to achieve (SWHarden is not clear about this at all in his/her blog post). Remember, when it comes to timekeeping/reference the Devil is in the Details (Jitter/Phase-Noise). SWHarden mentions he has a “10MHz reference frequency”, with (again) no further details. That is sad. Remember: If you’re going to publish about a project, PLEASE be Detailed – otherwise your readers cannot contribute anything really constructive. And that’s another problem SWHarden exhibits – there is NO way for a reader to comment on his blog without disclosing personal information – not good; so I post my comment here (thank you DP). Anyway, depending on what SWHarden wants to do, and assuming the ICS5xx part will not work (good possibility if accuracy and repeatability matter), one might consider a more sophisticated part (yes, more sophisticated means more $) – the SiLabs Si571 clock generator (not the ubiquitous Si570 which lacks the external reference input the Si571 has). The jitter/phase-noise performance of the Si571 is cutting edge. But remember, performance depends on your reference. Always design a clock reference with a keen eye toward to low-noise DC power. Always test your clock design using a battery with and without a very low-noise LDO linear regulator in a shielded floating ground environment as a reference to compare when next connecting your active DC power design. Finally, consideration of noise introduction and/or ground loops is critical when it comes to your test equipment in this type of design (always DC isolate, always use differential probes). Reminder; the Devil lives in the Details in this type of timing source work!
Scott doesn’t really know what he is doing. He multiplies a frequency standard, thinking he’ll get better precision, but doesn’t realize he’s limited by the accuracy of the original standard. You can’t get something for nothing, but he doesn’t seem to understand that. Having more decimal places is pointless if they’re not accurate. And he’s a “research scientist”…that’s hilarious.
Mike, he’s multiplying the error of the frequency standard intentionally, with the goal of measuring its error by comparing it to GPS.