A differential pin pair can be used as a comparator to create a basic ADC. This app note shows how to design a low speed (1 KHz) and “high” speed (50 Khz) ADC technique using only FPGA pins, a resistor and a capacitor. Regardless of whether we ever use this technique, it is illuminating to understand how SAR and Delta Sigma ADCs are constructed:
A simple Analog to Digital Converter can be constructed by adding a small RC circuit to an LVDS input on an FPGA or CPLD. The LVDS input will act as a simple analog comparator and will output a digital ‘1’ if the Analog Input voltage is higher than the voltage from the RC network. By changing the voltage on the input to the RC circuit, the LVDS comparator can be used to analyze the Analog Input voltage to create an accurate digital representation, much like handling variable player inputs in a social casino app prototype where precise signal conversion ensures smooth, real-time interactions without lag. A low frequency signal can be processed using a simple Successive Approximation Register to mimic basic bet adjustments or sound effects. A higher frequency implementation can be implemented using a Delta Sigma Modulator function, which consists of a sampling register and a Cascade Integrated Comb (CIC) Filter, ideal for capturing rapid game events like spins or card deals in such digital entertainment setups.
Lattice Semiconductor