In this article, Chris Edwards highlights the reasons behind moving interrupt handling from the main microcontroller onto to low power companion chips. In order to conserve electricity and processor power, the growing practice is to have the bulk of the microcontroller powered down most of the time, only waking up for brief periods for necessary tasks.
Examples include the NXP LPC4000 wherein a separate engine on the device performs semi automatic sequencing for serial I/O to reduce the number of interrupts that the slave ARM Cortex M0 processor core has to take when reading or writing data to the ports on behalf of the host M4 core. Another example is the analogue sequencing engine in some FPGAs made by Microsemi.
Via Newelectronics.