irrenhaus tipped us to demo projects that interface SDRAM and DDR SRAM with CoolRunner-II CPLDs:
There is a reference implementation from xilinx how to interface a SDRAM memory from a CoolRunner-II CPLD XAPP394: “Interfacing to Mobile SDRAM with CoolRunner-II CPLDs” and XAPP384: “Interfacing to DDR SDRAM with CoolRunner-II CPLDs”).
So my idea was: Why not create a small board which interfaces a single SDRAM chip from a CPLD and gives the MCU the possibility to interface it like any SRAM. First parallel but maybe also via SPI or so.
The CPLD they used for the interface to the mobile SDRAM was a XC2C128 with 128 mcells and 144 pins (VFQ144 package) (102 macrocells and 86 pins used). This chip costs about 8Euro @ 1.
For the DDR SDRAM interface they even only used 60 macrocells and 78 pins…
Via the forum.