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Topic: Discussion: Effects of right-angel bends and propagation delay in microstrips (Read 6142 times) previous topic - next topic

Discussion: Effects of right-angel bends and propagation delay in microstrips

//EDIT by IPenguin// This thread has been split from the Logic Sniffer v1.03 manufacturing update thread.

The discussion started over a right-angel bend in one of the USB signal traces of the OLS v1.03 redesigns (between USB connector and MCU pad) and evolved into the rather general field of propagation of signals along traces on PCBs (in particular but not limited to microstrip on FR-4 expoxy), in particular the influence of right-angel bends on such signals in dependence on their frequency and rise/fall times (slope).

//END EDIT//

[quote author="rsdio"]
(*) On that note, the differential data traces look great on the v1rev3 PCB except for one thing: RC4/D- has a single right-angle turn in it which should probably be a couple of 45-degree turns like all the rest. Also, you might consider increasing the width of the D+,D- traces to be almost as wide as the PIC pads. It's actually difficult to know the impedance of the traces without coordination with the PCB fab house, but generally "wider" is better. My general rule is to go about as wide as the SMD pads and not worry about going beyond that.
[/quote]
Do you have any references about a measurable effect of right-angle bends on signals in the USB range? All papers I've found that actually did measurements considered the effects insignificant up to at least 4GHz or so, both impedance mismatch and EMI. Most of the arguments against right-angle bends seem to be based on belief, so I'd be happy with some hard facts. Of course it doesn't hurt to minimize these effects.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #1
[quote author="alm"]Do you have any references about a measurable effect of right-angle bends on signals in the USB range? All papers I've found that actually did measurements considered the effects insignificant up to at least 4GHz or so, both impedance mismatch and EMI. Most of the arguments against right-angle bends seem to be based on belief, so I'd be happy with some hard facts. Of course it doesn't hurt to minimize these effects.
[/quote]
Part of the consideration is that even a low-frequency clock - e.g. USB Full Speed at 12 MHz - has fast rise and fall times, making it very similar to higher-frequency clocks.  In other words, square waves have an infinite series of harmonics, and thus act like high frequency.  I would like to see papers which actually measure this scientifically, but I am not aware of any.

One exception to the above are drivers which are slew limited.  Maxim has some RS-485 drivers which limit the bandwidth of their outputs, and thus get rid of a lot of harmonics.  However, these kinds of drivers are rare, so most clocks have harder edges.

Good references are from Texas Instruments, their SPRAAR7 and SDYA011, but I don't think they back up their recommendations with specific research papers.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #2
[quote author="rsdio"]
Part of the consideration is that even a low-frequency clock - e.g. USB Full Speed at 12 MHz - has fast rise and fall times, making it very similar to higher-frequency clocks.  In other words, square waves have an infinite series of harmonics, and thus act like high frequency.  I would like to see papers which actually measure this scientifically, but I am not aware of any.

One exception to the above are drivers which are slew limited.  Maxim has some RS-485 drivers which limit the bandwidth of their outputs, and thus get rid of a lot of harmonics.  However, these kinds of drivers are rare, so most clocks have harder edges.

Good references are from Texas Instruments, their SPRAAR7 and SDYA011, but I don't think they back up their recommendations with specific research papers.
[/quote]

I'm aware that 12Mhz clock rate does not imply 12MHz bandwidth for digital signals. But in the real world all drivers are slew limited in some way, it takes effort to get really fast rise times, why would a designer do that if it's not necessary. Plus it's not desirable for EMC purposes, you want the slowest edge rate that gets your signal across for EMC. I'm not that familiar with the USB spec, but this test report reports a host rise/fall time test that specifies >400ps, so that might be the maximum edge rate for compliant devices. I found some measurements elsewhere (USB 2.0 hi-speed) that measured a rise time of 500ps or so.

Right angle corners on printed circuit board traces, time and frequency domain analysis (M. Montrose, date?) concludes that signal integrity is only affected by the right-angle bends (in his test setup, which aren't very wide traces) if the edge rate is faster than 15ps. Microstrip right angle bends (Miller Techonlogy TN063) considers the reflection effects insignificant for striplines (wider traces) above 100ps with a dielectric thickness <10mil. Who's afraid of the big, bad bend (H. Johnson, 2000) considers right-angle bends insignificant for 100ps edge rates for an 8-mil 50ohm microstrip on FR-4, and suggests that it might become an issue with 10GHz serial buses (a lot faster than USB!).

If you're not using real controlled-impedance traces (probably not very cost-effective for a cheap project) and using standard FR-4, your trace impedance is unlikely to be exactly matched to the rest of your system, so the tiny disturbance of the impedance is even less significant (who cares about a 1% disturbance in a bend if there's a 20% disturbance after the USB connector)? I believe you suggested just ignoring the whole microstrip/controlled impedance stuff and make them as wide as the pads (not that I disagree), that's likely to disturb the signal a lot more than a few right-angle bends.

I read those TI appnotes, they're definitely useful guidelines for layout, and I'm sure you won't go wrong if you follow them, but they don't really give a justification.

My conclusion is that right-angle bends are probably not an issue with any of the current buses (especially USB 2.0 hi-speed which is one of the slowest of the current 'fast' buses), and certainly not for anything currently within reach of amateurs. But I'd love to be proven wrong and learn that all the arguments against right-angle bends for 'slow' signals are actually based on real facts as opposed to belief and cargo cult.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #3
Thanks for the scientific approach to this topic.  I plan on reading the links you provided.  I doubt I'll ever run across the answers that you originally asked for, but now that you've piqued my curiosity I'll be on the lookout for anything else I can find.

[quote author="alm"]I believe you suggested just ignoring the whole microstrip/controlled impedance stuff and make them as wide as the pads (not that I disagree), that's likely to disturb the signal a lot more than a few right-angle bends.[/quote]
How would it disturb things to remove the transition from trace width to SMD pad width?

I wasn't exactly suggesting to ignore the controlled stuff, but rather to try and do the best you can without the expense of paying the PCB shop for controlled impedance.  I assume that the width of the pads couldn't be too narrow or else the chip wouldn't be a good design, so I further assume that making the entire trace the same width as the SMD pads would be a decent metric.  Then again, the transition from pad to pin could easily be more of an issue than the trace to pad transition.

I think that I tried using an online calculator for controlled impedance, and plugged in the specifics from the PCB fab house that I was using.  I believe that I came up with a trace width that was wider than my SMD pads, not narrower, so my conclusion was that a reasonable compromise was to just make the traces as wide as possible - i.e. as wide as the SMD pads - and be done with it.  What I didn't want to do in that case was to make my traces wider than the SMD pads and then deal with making them narrower at the chip - seemed like a bad move based on an unvetted web site.

If I ever have a client with the budget for controlled impedance, then I would at least have the PCB fab houses that offer the service give it a go.  And I'd be paying close attention to see how they change what I started with.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #4
[quote author="rsdio"]
[quote author="alm"]I believe you suggested just ignoring the whole microstrip/controlled impedance stuff and make them as wide as the pads (not that I disagree), that's likely to disturb the signal a lot more than a few right-angle bends.[/quote]
How would it disturb things to remove the transition from trace width to SMD pad width?
[/quote]

I wasn't suggesting that your change would make the mismatch worse than the current design, just that it wouldn't get the impedance within a few percent or so that represents the mismatch from right-angle bends. Based on my understanding (I'm not an EE, just a science student with an interest in electronics): Assuming the rising edge (eg. 3*10^8 m/s / sqrt(0.475 * 4.3 + 0.67) * 400ps = 73mm, speed of light for epsilon = 4.3 with a simple approximation formula for a stripline) is much longer than the disturbance, you can model a disturbance just like an increase in distributed capacitance/inductance, so it will change the impedance of the transmission line (sqrt(L/C) for Z0), and cause a mismatch at the load. Most disturbances are shorter than 73mm, but possibly not by an order of magnitude if it's the whole trace, so I would be careful in this case. The longer the disturbance, the larger the change in capacitance/inductance (obviously). A section with an impedance mismatch in the opposite direction might compensate in this model. As the edges get shorter compared to the mismatch, you'll have to consider the distance between mismatches, since reflections at these mismatches might interfere with the rising/falling edge. So a mismatch at the pads is better than a mismatched impedance of the whole trace.

[quote author="rsdio"]
I wasn't exactly suggesting to ignore the controlled stuff, but rather to try and do the best you can without the expense of paying the PCB shop for controlled impedance.  I assume that the width of the pads couldn't be too narrow or else the chip wouldn't be a good design, so I further assume that making the entire trace the same width as the SMD pads would be a decent metric.  Then again, the transition from pad to pin could easily be more of an issue than the trace to pad transition.

I think that I tried using an online calculator for controlled impedance, and plugged in the specifics from the PCB fab house that I was using.  I believe that I came up with a trace width that was wider than my SMD pads, not narrower, so my conclusion was that a reasonable compromise was to just make the traces as wide as possible - i.e. as wide as the SMD pads - and be done with it.  What I didn't want to do in that case was to make my traces wider than the SMD pads and then deal with making them narrower at the chip - seemed like a bad move based on an unvetted web site.

If I ever have a client with the budget for controlled impedance, then I would at least have the PCB fab houses that offer the service give it a go.  And I'd be paying close attention to see how they change what I started with.
[/quote]

I'm sure you can get the same formulas from IPC-2221 or IPC-2221A if that makes you feel better ;). The trace width does depend on the distance from the ground plane. It's quite likely that most USB parts were developed with 4+ layer boards in mind, so the required trace width might be much larger for a two layer board with usually a much larger distance between the planes. A tiny impedance mismatch at the pads isn't that significant. It's possible that the mismatch at the solder connections are more significant than the mismatches on the PCB (connections are always tricky), but I'm sure they're within the USB specs, which considering that it was developed for cheap consumer electronics, is probably not too strict. Plus impedance mismatches are cumulative (unless they happen to be in opposite direction), so if both are about the same magnitude, you've just made it twice as worse.

My argument isn't that you're doing something wrong, just that there are probably a few things that are much more significant than those right-angle bends, so it's not really worth worrying about those until you've fixed those (use real controlled impedance traces and possibly something better than FR-4). Assuming your traces are thinner than necessary for a microstrip with the correct impedance, the extra capacitance might actually decrease the total mismatch, since your traces are too inductive ;). Although not enough to make a difference.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #5
[quote author="alm"]
[quote author="rsdio"]
[quote author="alm"]I believe you suggested just ignoring the whole microstrip/controlled impedance stuff and make them as wide as the pads (not that I disagree), that's likely to disturb the signal a lot more than a few right-angle bends.[/quote]
How would it disturb things to remove the transition from trace width to SMD pad width?
[/quote]

I wasn't suggesting that your change would make the mismatch worse than the current design, just that it wouldn't get the impedance within a few percent or so that represents the mismatch from right-angle bends. Based on my understanding (I'm not an EE, just a science student with an interest in electronics): Assuming the rising edge (eg. 3*10^8 m/s / sqrt(0.475 * 4.3 + 0.67) * 400ps = 73mm, speed of light for epsilon = 4.3 with a simple approximation formula for a stripline) is much longer than the disturbance, you can model a disturbance just like an increase in distributed capacitance/inductance, so it will change the impedance of the transmission line (sqrt(L/C) for Z0), and cause a mismatch at the load. Most disturbances are shorter than 73mm, but possibly not by an order of magnitude if it's the whole trace, so I would be careful in this case. The longer the disturbance, the larger the change in capacitance/inductance (obviously). A section with an impedance mismatch in the opposite direction might compensate in this model. As the edges get shorter compared to the mismatch, you'll have to consider the distance between mismatches, since reflections at these mismatches might interfere with the rising/falling edge. So a mismatch at the pads is better than a mismatched impedance of the whole trace.[/quote]

I am a bit confused here. Is your equation
Quote
3*10^8 m/s / sqrt(0.475 * 4.3 + 0.67) * 400ps = 73mm

a simplified calculation of the wavelength for a signal with a frequency of 1/400ps (2,5 *10^9 s^-1 or 2.5GHz) in a Cu or Al trace (conductor) on FR-4 (dielectric)?

Just curious because I don't understand the values in the part under the square root of the equation (0.475 * 4.3 + 0.67) ... just guessing that 4.3 is the dielectric constant for FR-4 (you picked a value (4.3) at the lower end in the range usually given for FR-4 (epoxy) in the literature for FR-4,  4,2 ... 4,9)?

For the OLS we don't have to guess for the USB rise/fall times because Microchip specifies USB low-speed and full-speed timing requirements - min and max transition rise and fall times - for the PIC18F26J50's USB signals :)

For USB Full-Speed (the timing requirements for USB Low-Speed would result in an even longer wavelength)

- TFR Transition Rise Time min 4 ns and max 20 ns with CL = 50 pF
- TFF Transition Fall Time min 4 ns and max 20 ns with CL = 50 pF
(Microchip, PIC18F46J50 Family Data Sheet (DS39931C), p. 523

I estimate a wave length of 580mm for a 250MHz signal (using the min rise/fall time of 4 ns for the frequency and 4,3 for Er, i.e. FR-4).

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #6
[quote author="IPenguin"]
I am a bit confused here. Is your equation
Quote
3*10^8 m/s / sqrt(0.475 * 4.3 + 0.67) * 400ps = 73mm

a simplified calculation of the wavelength for a signal with a frequency of 1/400ps (2,5 *10^9 s^-1 or 2.5GHz) in a Cu or Al trace (conductor) on FR-4 (dielectric)?
[/quote]
I found Microstrip propagation times: slower than we think. It gave 0.475 * espilon_r (k) + 0.67 as the traditional formula for the effective dielectric constant for a microstrip (since it's a mix of air on one side and PCB substrate on the other side), and then went on to develop a more complex model. I was perfectly happy with the simple, traditional formula ;). Then I just used c / sqrt(epsilon_r) for the propagation speed. I assume the constants were based on an empirical or numerical model (did they use those back then?), but didn't actually read the 1967 paper.

[quote author="IPenguin"]
Just curious because I don't understand the values in the part under the square root of the equation (0.475 * 4.3 + 0.67) ... just guessing that 4.3 is the dielectric constant for FR-4 (you picked a value (4.3) at the lower end in the range usually given for FR-4 (epoxy) in the literature for FR-4,  4,2 ... 4,9)?
[/quote]
4.3 is indeed the dielectric constant of FR-4. I initially used propagation speed figures from the Montrose article I cited earlier, but he screwed up the conversion between m and inch, and I think both were higher than the light speed in vacuum ;). I hope that's the only mistake he made. He used 4.3, so I did, too. Something like 4.6 might be closer to reality, but it doesn't really matter, since my argument was about orders of magnitude.

[quote author="IPenguin"]
For the OLS we don't have to guess for the USB rise/fall times because Microchip specifies USB low-speed and full-speed timing requirements - min and max transition rise and fall times - for the PIC18F26J50's USB signals :)

For USB Full-Speed (the timing requirements for USB Low-Speed would result in an even longer wavelength)

- TFR Transition Rise Time min 4 ns and max 20 ns with CL = 50 pF
- TFF Transition Fall Time min 4 ns and max 20 ns with CL = 50 pF
(Microchip, PIC18F46J50 Family Data Sheet (DS39931C), p. 523

I estimate a wave length of 580mm for a 250MHz signal (using the min rise/fall time of 4 ns for the frequency and 4,3 for Er, i.e. FR-4).
[/quote]
Yep, full-speed USB (did they shoot the inventor of that name yet?) will be a lot slower. According to the above calculation, it would be about 730mm. You probably used c/sqrt(4.3), but that's if the conductor is fully surrounded by FR-4. Not that it really matters, as mentioned above, it's mainly about orders of magnitude, so we might as well use 600mm. So any disturbances below 60mm or so can be treated as slight changes to the L or C of the transmission line, as opposed to individual features. The size of square corners is a few orders of magnitude smaller than this (.6mm or so? depending on trace width).

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #7
Thank your for the details and pointing me at Douglas Brooks articles. :)

Since I rather come from the silicon side than from the PCB, antenna, transformer or connector side I am not too proficient on how PCB technology and the specific models evolved (the difference is that in silicon design there's usually a dielectric below and above the conductor while in PCB you have "air" above the microstrip unless we look at "embedded" microstrips). However, microstrip interconnects are very common in integrated circuits - again no air above the upper microstrip because the metal layers are usually "overglassed". Essentially

  ε[sub:]eff[/sub:] = 0.475 * ε[sub:]r[/sub:] + 0.67

describes the relative effective permittivity of a microstrip according to one model developed by H. R. Haugg and published in "Characteristics of microstrip transmission lines," IEEE Trans. Energy Conversion, Vol. 16, No. 2, 185, 1967. It's an empirical formulae based on certain assumptions - for more details we'd have to take a look at the original paper. To my knowledge numerical electromagnetic (NE) modeling techniques did not exist before the early 1970's (not before there were CDC and Cray mainframe number crunchers) - see "Survey of Numerical Electromagnetic Modeling Techniques" by Todd H. Hubing, Dept. of Electrical Engineering, University of Missouri-Rolla, published September 1, 1991.

I found a quite interesting paper by S. R. Nelatury1, M. N. O. Sadiku, and V. K. Devabhaktuni, "CAD Models for Estimating the Capacitance of a Microstrip Interconnect: Comparison and Improvisation" published in PIERS Proceedings, August 27-30, Prague, Czech Republic, 2007. It compares 12 CAD models (based on empirical formulae) and a number use different models for ε[sub:]eff[/sub:] which postulates different propagation velocities in the same media.

I remember to have used

  ε[sub:]eff[/sub:] = (ε[sub:]r[/sub:] + 1)/2 + (ε[sub:]r[/sub:] -1)/2 * (1 + w/10t)^-1 

by Kumar et al. but I don't remember in what exact context. In the end all models mentioned in the above paper are based on empiric formulae and are only valid for certain frequency ranges, temperatures etc. In the late 80s I performed measurements in a research project on switching characteristics of CMOS transistors and gates at very low temperatures (first we engulfed CMOS chips - 4049 inverters/buffers and 4011 quad NANDs - in liquid nitrogen and later in helium) ... none of the previously existing models did match the results that were gained from the experiments ... actually most models predicted that CMOS gates would not switch below 40°K or so at all ... they switched like hell :D

Quote
Temperature range

Conventional CMOS devices work over a range of −55 °C to +125 °C. There were theoretical indications as early as August 2008 that silicon CMOS will work down to 40 kelvins, or −233 °C.[2] Functioning temperatures near 40 kelvins have since been achieved using overclocked AMD Phenom II processors with a combination of liquid nitrogen and liquid helium cooling. [3]

I'd really like to continue this discussion but due to lack of time on my side and realizing that my English has deteriorated too much over the last couple of years to make this an easy task I will make short comments from now on ...

1. I agree, regarding the right-angel bend a wavelength of +/-25% is more than sufficient to determine if the bend has a significant influence on the signal or not

2. ε[sub:]r[/sub:] is usually given for room temperature (18°C) and frequencies between 50Hz and 100kHz - it varies with the temperature and the frequency ;)

3. width, length, and thickness of the trace have a by magnitudes greater (and measureable) influence on L and C at 12MHz than the 90° bend

Re: Discussion: Effects of right-angel bends and propagation delay in microstrip

Reply #8
By the way, it was mentioned elsewhere on this site (in another thread) that the above discussions have "concluded" that right angle bends in USB traces are of no concern.  I just want to point out that this goes contrary to every discussion I've heard elsewhere.

The reason given most often concerns reflections. I am told that termination of USB differential data, like any other bus, is important to reduce reflections that would cause misreading of logic levels.

The "conclusions" above talk about impedance changes, but I don't quite follow the math well enough to be convinced that there would be no reflections. Whenever there are reflections, it's possible to misread a logic level because several reflections of the original voltage add and subtract. Personally, I used the Eagle feature which allows curved traces for USB data lines, thus avoiding 90-degree and 45-degree turns. Truth is that I cannot prove that it is necessary, but I can say that it doesn't cost any extra - even if it is more superstition than science. What initially alerted me to be concerned was how the USB specifications make it sound like it is so easy to screw up USB, as if the data is very fragile. I got the impression that even a non-sanctioned cable could cause the whole system to fail.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #9
rsdio, the "other" thread was split and the discussion about microstrip "models" and the influence of various factors and variables on signals in/along traces moved here - I think this is the split-off of the very same thread you have in mind (see EDIT in the first post of this thread).

The changes in above talk about (essentially) ε[sub:]eff[/sub:] are caused by the different models or more precise the different assumptions the models are based on.
Since line impedance of both stripline and microline is directly related to ε[sub:]r[/sub:] and depending on the model used for ε[sub:]eff[/sub:] we are back at the same general problem. For the "Kaupp" model the equation for microstrip line impedance is:

  Z[sub:]0[/sub:] = 60/sqrt(0.475 * ε[sub:]r[/sub:] + 0.67) * ln(4h/(0.67 * (0.8w + t))

The math for line impedance, differential impedance, loaded impedance, C[sub:]0[/sub:], L[sub:]0[/sub:], unterminated stub length, reflection coefficient and reactance frequency for microstrip and stripline is summarized in National Semiconductors application note 905 written by James A. Mears with examples.

Douglas G. Brooks explains differential impedance and design rules for differential signals in his Differential Signal Articles. He wrote a very comprehensive article on "Why Do Authors and Seminar Leaders Disagree?" (on design guidlines) ;)

To this point I have not attempted to calculate the line impedance of the USB traces on the OLS v1.03 redesign - I trust the USB spec takes care of cable length, impedance and termination, respectively the Microchip PIC USB interface design takes care of it as described in section 21 of the PIC18F46J50 FAMILY data sheet as long as l << λ applies for the length of the USB data traces on the board. λ for 12MHz (USB full-speed) can be approximated to about 41m (!) using the previously mentioned equation

  λ = c[sub:]0[/sub:]/f * 1/sqrt(0.475 * ε[sub:]r[/sub:] + 0,67)

The length of the USB onboard signal traces is about 0,02m, w < h applies and as far as I can see, no plane boundaries or signal lines are crossed or run parallel with over a significant distance. This makes me believe that I can switch into denial mode :D

If we look at USB high-speed signals the situation looks a bit different, so.

Re: Discussion: Effects of right-angel bends and propagation delay in microstrips

Reply #10
[quote author="IPenguin"]
Since I rather come from the silicon side than from the PCB, antenna, transformer or connector side I am not too proficient on how PCB technology and the specific models evolved (the difference is that in silicon design there's usually a dielectric below and above the conductor while in PCB you have "air" above the microstrip unless we look at "embedded" microstrips). However, microstrip interconnects are very common in integrated circuits - again no air above the upper microstrip because the metal layers are usually "overglassed".
[/quote]
Isn't that a stripline? Or is it without the ground plane on the top?

[quote author="IPenguin"]
 Essentially

  ε[sub:]eff[/sub:] = 0.475 * ε[sub:]r[/sub:] + 0.67

describes the relative effective permittivity of a microstrip according to one model developed by H. R. Haugg and published in "Characteristics of microstrip transmission lines," IEEE Trans. Energy Conversion, Vol. 16, No. 2, 185, 1967. It's an empirical formulae based on certain assumptions - for more details we'd have to take a look at the original paper.
[/quote]
The paper likely contains some assumptions that may not be valid in this case. On the other hand, I believe the Brooks article referred to it as traditional, so it might be widely applicable. Or it was just the easiest solution ;). "There is always an easy solution to every human problem—neat, plausible, and wrong." -- H.L. Mencken

[quote author="IPenguin"]
To my knowledge numerical electromagnetic (NE) modeling techniques did not exist before the early 1970's (not before there were CDC and Cray mainframe number crunchers) - see "Survey of Numerical Electromagnetic Modeling Techniques" by Todd H. Hubing, Dept. of Electrical Engineering, University of Missouri-Rolla, published September 1, 1991.
[/quote]
I think that should be Survey of Numerical Electromagnetic Modeling Techniques. That confirms my suspicion that numerical modeling was not feasible without powerful computers.

[quote author="IPenguin"]
I found a quite interesting paper by S. R. Nelatury1, M. N. O. Sadiku, and V. K. Devabhaktuni, "CAD Models for Estimating the Capacitance of a Microstrip Interconnect: Comparison and Improvisation" published in PIERS Proceedings, August 27-30, Prague, Czech Republic, 2007. It compares 12 CAD models (based on empirical formulae) and a number use different models for ε[sub:]eff[/sub:] which postulates different propagation velocities in the same media.
[/quote]
Thanks for the link! Kaupp performs pretty horrible in that, not surprising since it's the oldest citation in that article and microstrips were probably pretty new back then. Schneider seems to have improved it a lot, however, and was only published two years later.

[quote author="IPenguin"]
In the end all models mentioned in the above paper are based on empiric formulae and are only valid for certain frequency ranges, temperatures etc. In the late 80s I performed measurements in a research project on switching characteristics of CMOS transistors and gates at very low temperatures (first we engulfed CMOS chips - 4049 inverters/buffers and 4011 quad NANDs - in liquid nitrogen and later in helium) ... none of the previously existing models did match the results that were gained from the experiments ... actually most models predicted that CMOS gates would not switch below 40°K or so at all ... they switched like hell :D
[/quote]
You can't expect to extrapolate empirical models way beyond the original conditions, so I'm not surprised that most of them failed horribly. Must have been fun :).

[quote author="IPenguin"]
1. I agree, regarding the right-angel bend a wavelength of +/-25% is more than sufficient to determine if the bend has a significant influence on the signal or not

2. ε[sub:]r[/sub:] is usually given for room temperature (18°C) and frequencies between 50Hz and 100kHz - it varies with the temperature and the frequency ;)

3. width, length, and thickness of the trace have a by magnitudes greater (and measureable) influence on L and C at 12MHz than the 90° bend
[/quote]
Agreed with all that. Certainly FR-4, which isn't exactly known for great high-frequency characteristics, will probably have a different dielectric constant at 1GHz.

[quote author="rsdio"]
By the way, it was mentioned elsewhere on this site (in another thread) that the above discussions have "concluded" that right angle bends in USB traces are of no concern.  I just want to point out that this goes contrary to every discussion I've heard elsewhere.
[/quote]
I've also often heard the statement "don't use right-angle bends for fast circuits", even if fast was an I[sup:]2[/sup:]C bus with a really slow risetime because it's open-collector with just a 4.7k or so pull-up and lots of capacitance. I've never seen data or calculations why, however. I've found articles by three different people (including the well-respected Howard Johnson) that conclude from actual data that the bends are insignificant up to a few GHz or so. Admittedly, only Montrose did the actual measurements, the other were purely theoretical, but their arguments seem sound to me.

[quote author="rsdio"]
The reason given most often concerns reflections. I am told that termination of USB differential data, like any other bus, is important to reduce reflections that would cause misreading of logic levels.
[/quote]
And reflections are caused by impedance mismatches, so talking about impedance mismatch is the same as talking about reflections (except that reflections can be improved by making the transmission line lossy (add resistance), but that's not practical on a PCB, and probably outside the USB spec).

[quote author="rsdio"]
The "conclusions" above talk about impedance changes, but I don't quite follow the math well enough to be convinced that there would be no reflections. Whenever there are reflections, it's possible to misread a logic level because several reflections of the original voltage add and subtract.
[/quote]
That's only if the rising/falling edge is shorter than the bend. In this case, the wave is almost two orders of magnitude longer than the bend, and more than an order of magnitude longer than the PCB trace. So the edge is still rising when it meets the reflection, and it will only increase the rise time by a (probably) insignificant amount.

[quote author="rsdio"]
Personally, I used the Eagle feature which allows curved traces for USB data lines, thus avoiding 90-degree and 45-degree turns. Truth is that I cannot prove that it is necessary, but I can say that it doesn't cost any extra - even if it is more superstition than science. What initially alerted me to be concerned was how the USB specifications make it sound like it is so easy to screw up USB, as if the data is very fragile. I got the impression that even a non-sanctioned cable could cause the whole system to fail.
[/quote]
The impedance might be quite critical, so a cable with the wrong impedance might screw it up. The change of impedance by right angle bends is negligible according everything we've seen in this thread. I agree that it doesn't hurt, as long as you have the PCB space. Curved traces certainly won't perform any worse.

[quote author="IPenguin"]
To this point I have not attempted to calculate the line impedance of the USB traces on the OLS v1.03 redesign - I trust the USB spec takes care of cable length, impedance and termination, respectively the Microchip PIC USB interface design takes care of it as described in section 21 of the PIC18F46J50 FAMILY data sheet as long as l << λ applies for the length of the USB data traces on the board. λ for 12MHz (USB full-speed) can be approximated to about 41m (!) using the previously mentioned equation

  λ = c[sub:]0[/sub:]/f * 1/sqrt(0.475 * ε[sub:]r[/sub:] + 0,67)

The length of the USB onboard signal traces is about 0,02m, w < h applies and as far as I can see, no plane boundaries or signal lines are crossed or run parallel with over a significant distance. This makes me believe that I can switch into denial mode :D
[/quote]
Shouldn't you use the highest frequency component (rise/fall time) for that calculation, i.e. that 4ns or so? Either way, the PCB trace is much shorter. Just a note that the impedance of the PCB trace does affect the total capacitance/inductance of the transmission line, even if it does not cause individual reflections. So if the PCB trace has twice the impedance compared to the USB cable, and it's 10% of its length (admittedly a pretty short cable in this case), the total impedance would be 10% off if the original cable was bang-on (and more if the cable happened to be on the high side). So it might not hurt to try to get it somewhat close to correct, but that's just about trace width and height, not about minor <=1% details.

 

Re: Discussion: Effects of right-angel bends and propagation delay in microstrip

Reply #11
Since I sort of started this thread by complaining about the PCB routing, I want to follow up with a brief comment.  I haven't actually studied all of the math mentioned above, but I'm sure that I will some day want to read all of the linked articles, so thanks everyone!

Just to explain, the primary reason that I complained about the right-angle was that it was only in one trace out of a differential pair.  The Douglas Brooks articles mention that it is important for common-mode rejection to keep the two traces of a differential pair close together, with similar routing, and the same length.  I suppose that means you could have a right angle so long as both traces following the same right angle.  However, the length of the traces would differ more when using right angles than when using gentler angles or even curves.  Another reason for my complaint was that the right angle really was not necessary for any reason that I could see.

I'm glad that this thread was split out from the one where I initially made my comment.  I've certainly learned a thing or two, and I'm sure I will learn more as I revisit this thread in the future.