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Topic: XT-IDE adapter with CPLD builds (Read 192669 times) previous topic - next topic

XT-IDE adapter with CPLD builds

Exciting progress on the XT-IDE PCB: ... controller

Hey ian,

Today i was able to synthesizing the sources for the CPLD but i found a couple of bugs in the PCB's and CPLD sources.

In both PCB's (v1 and v1a) the "8bit<->16bit IDE mux" is not connected to the CPLD, on the v1 board not all the power pins of the CPLD are connected so if fixed the schematics but the PCB needs some jumpers.

Also the CPLD sources included the ROM decoder with is on the PCB as IC2 so i removed that part from the schematics.

I have put everything together in a zip file on my private server, including the programming files for 3 different CPLD's, the XC9536 for the v1 board and the XC9536XL and XC9572XL for the v1a board.

You can find the zip file here, of course its under the same license as the original file so maybe you can give it better place on your google code side or the wiki.

HI Pietja,

Wow! fantastic work. It's great to see this project come to life after a year on the shelf. I am sorry about our mistakes on the PCB.

Thank you for the source and updates, I have commited them to SVN. Would you like SVN access?

I did not yet look at the fit report - did it fit well in teh 36 macrocell version? If so, then the 5volt CPLD could be used after all. On the other hand, if the 3v3 works we can use the 100-144 pin version and implement the other logic in it too for easier routing.

My I please copy this to the forum? It would be nice to have a public record of the development on this project, and notes for the other testers.

Please send a picture after you stuff the PCB, I'll run it on the blog and add it to the wiki documentation.

Thanks again, and best regards,



Personally i never used SVN so i don't know how to use it but that is something new to learn, access for when i know how to use it would be nice.

It fits just fine in a 36 macrocell CPLD the reports says the following:
Macrocells Used: 13/36 (37%)
Pterms Used: 84/180 (47%)
Registers Used: 0/36 (0%)
Pins Used: 31/34 (92%)
Function Block Inputs Used: 35/72 (49%)

According to the latest datasheet from Xilinx there was never a 5v XC9572 in TQFP package only a PLCC.

And of course you can put all this on the forums and the blog its an open source project after all ;)

btw i'm just back from work and the PCB was delivered today so tomorrow i will order the last parts from Farnell and if all goes well i will post the pictures this weekend.

Got a question? Please ask in the forum for the fastest answers.

Re: XT-IDE adapter with CPLD builds

Reply #1
Hi there, I'm going to contribute to this project too. This first message to avoid the nasty spam filter :-)

Re: XT-IDE adapter with CPLD builds

Reply #2
I just put two screenshots of the PCB's showing the disconnected traces in the SVN.
5V v1 screenshot with 7 unrouted traces.
3V3 v1a screenshot with 5 unrouted traces.

On the 5V v1 PCB you also need to connect pin 17 and 25 of the CPLD to the ground plane, this didn't show on the eagle screenshots. So the total unrouted traces on the manufactured PCB is 9.

Re: XT-IDE adapter with CPLD builds

Reply #3
OK that's easy to patch with wires. Have you made any further test ?

Re: XT-IDE adapter with CPLD builds

Reply #4
Today i ordered the last parts from farnell so i haven't been able to test it yet, i hope to get the missing parts tomorrow so i can test everything this weekend.

I also need to replace the CMOS battery on the mainbord because it have been leaking.

Re: XT-IDE adapter with CPLD builds

Reply #5
Thank you all for being involved on this project. I,m sorry about the spam filter, its the best we,ve found. Please leave any requests here, and we,ll roll them into the next pcb.
Got a question? Please ask in the forum for the fastest answers.

Re: XT-IDE adapter with CPLD builds

Reply #6
Today i finished building the XT-IDE adapter v1a PCB, the jumpers where a bit hard to do but everything is on the board now and the CPLD has been programmed.
Tomorrow i will test the board, the PC needs some fixes first.

For the next PCB design i would be nice if the onboard activity led and the external one get a separate series resistor so they are not directly connected in parallel.

Also the IDE connector could be rotated 180° so a normal angled connector can be used instead of the one i used where i manually flipped all the pins around.

And if we are messing with the IDE connector we could connect pin 20 to 5V so a disk on module can be powered from this pin directly.

Re: XT-IDE adapter with CPLD builds

Reply #8

I received a board today (thanks!) - unfortunately I'm a few steps behind so just ordering up the parts now.

Sorry if this is a noob question but what is the best way to program the CPLD?

Many thanks,

Re: XT-IDE adapter with CPLD builds

Reply #9
I used the Xilinx Platform Cable USB II from work, how to program it another way i don't know maybe a Bus Pirate or a Bus Blaster can do it.

The EEPROM i programmed with a cheep universal programmer from eBay, but it should be possible to program it on the pc with the tools from XTIDE Universal BIOS.

Re: XT-IDE adapter with CPLD builds

Reply #10
Thanks, OK so bus pirate solves that.  Next problem seem to be supply of these parts... stuck on the XC9572VQ44 and the EPROM already (in the UK).

Re: XT-IDE adapter with CPLD builds

Reply #12
Thanks very much indeed for posting these links - very much appreciated.  The board I have here is identical to that pictured above (Sep-2010 on bottom left)... this is a 5V board?

Re: XT-IDE adapter with CPLD builds

Reply #13
The difference between the boards is an extra 3.3V regulator in the top left corner next to the CPLD.
v1a is 3.3V and v1 is 5V, they both have Sep-2010 on them.

The wiki shows both so you can compare the two.

So if you PCB haves an regulator there you need an 3.3V CPLD (XC9536XL or XC9572XL) and the regulator.
If its not there you only need the 5v CPLD (XC9536).

Re: XT-IDE adapter with CPLD builds

Reply #14
I have tested the board today and it didn't go well :(

First i started the pc without the board to see if it can boot from a floppy, that went well.

Then i placed the board in the expansion slot and started the pc, no smoke :p but the bios came up with an error that the system setup was changed ?
The error was that both serial ports, the parallel port and the floppy controller were just gone :( so nowhere to boot the pc from.

Ok thats a big problem, next to see if the XTIDE bios worked so i placed the eeprom in an ethernet card as bootrom, ok now i can see the XTIDE bios :)

Back to the XT-IDE adapter with is made up of two parts, the BIOS with address decoder and the IDE interface itself.

To test if the bios and address decoder worked i placed a bit of tape over the read/write pins to the IDE interface so it was disabled, now i can still see the XTIDE bios on the XT-IDE adapter and i got my ports and floppy back :)

So the error was in the IDE interface part of the board, i went back to the CPLD because i had a bit of a issue connecting the address decoder with haves two bus connections and the rest of the circuits haves individual nets with other names.

To see if the problem was with the address decoder i replaced the Xilinx macro with an 74x521 symbol with don't haves bus connection but individual pins.

Everything synthesizing fine and i tried to put it in the CPLD with UrJTAG and a FT2232 interface but UrJTAG gave an error at 99% :(

So i removed the tape from the XT-IDE adapter hoping it might work now,
the pc started the same as with the tape on the adapter, first came the mainboard bios an the the XTIDE bios, the XTIDE bios was scanning the address where the XT-IDE adapter with harddisk should be, but found nothing :(

I went to the wiki of the original project to see if both schematics were the same, with they are.
Also on there wiki is an zip file with some utilities for the XT-IDE adapter, but those utilities also didn't find the IDE interface :(

So i think that the CPLD didnt program right or that there is still something wrong with the sources.

Because i don't have another programmer at home i have to wait until monday to program the CPLD with the official Xilinx programmer to see if that will make things work.