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Topic: BBv2 CPLD jtagkey implementation (Read 11495 times) previous topic - next topic

BBv2 CPLD jtagkey implementation

Didn't hear back any further from the list. I designed a JTAGkey implementation for the CPLD (image attached), the files are in SVN:
http://code.google.com/p/dangerous-prot ... %2FJTAGkey

I will assign the pins tomorrow and test out the new design.
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Re: BBv2 CPLD jtagkey implementation

Reply #1
SRST needs to be tristate too, just fixed that.
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Re: BBv2 CPLD jtagkey implementation

Reply #2
Latest design for the CPLD is in SVN. I believe the pin assignments are correct. It fits fine without any serious warning. I still need to export the XSVF and test it, which I hope to do tomorrow but it might be after the new year.

PS: BBv1 will be on sale any moment. The FT2232 breakout board is available today if you want a 3.3volt JTAG-able board now.
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Re: BBv2 CPLD jtagkey implementation

Reply #3
Exported the SVF and programmed it with BBv1. Everything went without a hitch the first time, even the CPLD design worked straight away. Used the BBv2 to chain scan a CPLD board without a problem. Nice!

I connected it to it's own JTAG header. It chain scanned, but things fell apart before a programming finished :)

Attached are:
*Self-programming screenshot
*CPLD schematic
*synthesis report

There's lots more hello-world screen-shots, programming instructions, etc, on the design notes page:
http://dangerousprototypes.com/docs/Cla ... Blaster_v2

SVF and ISE project for the CPLD are in SVN.

I think there is a minro bug with teh target present circuit, it always seems to glow dimly. Will check that out next.
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Re: BBv2 CPLD jtagkey implementation

Reply #4
Just a friendly note if you're following this topic...

I split the monster Bus Blaster v2 thread into several small parts that should be easier to surf, but you will not get more notifications until you comment or click 'notify' on the new threads.

Bus Blaster v2 design thread http://dangerousprototypes.com/forum/in ... pic=1490.0
BBv2 CPLD design and implementation http://dangerousprototypes.com/forum/in ... pic=1659.0
urJTAG for BBv2 JTAG B http://dangerousprototypes.com/forum/in ... pic=1655.0
UART on BBv2 MSSPE2? http://dangerousprototypes.com/forum/in ... pic=1656.0
FT2232H EEPROM discussion http://dangerousprototypes.com/forum/in ... pic=1658.0
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Re: BBv2 CPLD jtagkey implementation

Reply #5
Can you fix the schematic a bit? You need to add pullups to FT_nSRST_BUF and FT_nTRST_BUF. (probably also FT_JTAG_BUS - but not confirmed)

I was having strange behavior on one of my boards. The cpu stayed in reset all the time, and one way to fix it was to tell OpenOCD to use push_pull on the reset line, or to add these pullups.

Attached is fixed svf (renamed as txt)

Re: BBv2 CPLD jtagkey implementation

Reply #6
Thank you for testing, great catch. Something like this? Did you update the schematic to make the attached SVF? I hope to make a vhdl version so it is easier to work in SVN, but the current source is there.
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Re: BBv2 CPLD jtagkey implementation

Reply #7
Exactly like that! I will test it some more in the evening.

Re: BBv2 CPLD jtagkey implementation

Reply #8
Synthesized and tested. Added to SVN. My svf is attached.
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Re: BBv2 CPLD jtagkey implementation

Reply #9
it seems to have the same problem, my compiled version doesn't. I guess it is caused by different "default" setting.

I have created new project of the same implementation but in vhdl, by default all input pins are FLOAT, and changed to pullup in .ucf. (default is set in "Fit" settings). As explained HERE

I have cleaned the project before zipping, so only the necessary parts are present. (project main file, vhdl, ucf, and svf)

Re: BBv2 CPLD jtagkey implementation

Reply #10
Nice VHDL, very clean and easy to read.

Quote
You can use the following UCF constraint to enable pull-ups:
net datain pullup;

You can use the following UCF constraint to enable bus-hold (keeper) circuitry:
net datain keeper;

This is easy enough, but I'm a little disappointed because it would have made such a good demo to show the flexibility and ease of schematic entry for beginners. I'm going to mess with it to see if I can get any pullups anywhere using the schematic entry.
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Re: BBv2 CPLD jtagkey implementation

Reply #11
While looking for the global pullup setting, I noticed that I had the wrong device selected (XA2C32A). I don;t know if the automotive range is just a temperate difference, or what, but maybe that was the issue? I'm surprised it worked at all.

Here is an updated version. Could you please test it if you have a chance? I'll do some experimentation with the breakout pins next.
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Re: BBv2 CPLD jtagkey implementation

Reply #12
I would guess that automotive parts will have different temperature range, maybe different power requirements. The internal structure might be the same.

You can use the schematic as demo, just be sure to set in "Fitting settings" (right click on the "FIT" on left pane) the default input termination to float. Then you can use pullup and it doesn't necessarily be in the ucf file. It can also be in the schematic. The default termination value is keeper, which doesn't work with pullup. (the pullup gets ignored and warning is printed).

I have tested the image, and it does have the same problem.

Re: BBv2 CPLD jtagkey implementation

Reply #13
Quote
The default termination value is keeper, which doesn't work with pullup. (the pullup gets ignored and warning is printed).

Thanks for spelling it out for me. I knew from reading other things that only pullup or keeper could be used in the device at once (mutually exclusive). I did not realize that keeper was enabled by default.

I changed the project settings, an updated svf is attached with all pins to floating.
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Re: BBv2 CPLD jtagkey implementation

Reply #14
Regarding your your discussion on the DBGACK signal, you could have a look on that MumJTAG Chinese project.
I cannot add the URL but it's easy to find all files (gerber, bom, ept etc ...) by googeling MumJTAG.
Hope it can help.