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Topic: UART on BBv2 MSSPE 2? (Read 7211 times) previous topic - next topic

UART on BBv2 MSSPE 2?

Random question.

Does the use of the second port on the FT chip preclude having it act like the Ti ICDI which uses the same FT chip to do JTAG + UART?

I read a bunch of the V1 thread at one point, it would be nice to have either converter boards or blank areas on the PCB for other standard JTAGs (10 pin).

Re: UART on BBv2 MSSPE 2?

Reply #1
Maybe. It depends on keeping the JTAG port of the CPLD in hiz state. Maybe with proper device support we can hold TMS steady and it will be possible. The RX and TX pins are shared with JTAG and available on the CPLD JTAG header.

JTAG seems to be a mess. I actually just use 1 to 1 female cables to connect to various devices. CPLDs and FPGAs often use a 6x1 or 5x1 header, ARM will use a 2x5, 2x8, 2x10, etc header.
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Re: UART on BBv2 MSSPE 2?

Reply #2
I agree it is a mess. I should have said I was talking about the Luminary Micro ICDI, it was designed before Ti purchased the company. I figured it would be tricky as the schematics for the ICDI use the second port on the FT to do the UART.

Re: UART on BBv2 MSSPE 2?

Reply #3
I guess one could put a tri-state buffer in to free the CPLD programming port for another use unless some enable is set. But that might just be a waste of money for most people.

IE http://www.nxp.com/documents/data_sheet ... CH245A.pdf (0.15 cents) to let the second port on the FTDI be free when not reprogramming the CPLD?

Re: UART on BBv2 MSSPE 2?

Reply #4
That's a great idea, thanks! 74 chips are so cheap, it's almost free if there's board space. If we have our own device driver in urJTAG we can use one of the extra pins to activate the buffer when the CPLD is being updated. Then the next revision could have 1x JTAG and 1x serial, or 2x JTAG, etc. Thanks for sharing.
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Re: UART on BBv2 MSSPE 2?

Reply #5
My thoughts exactly you can give everyone a free FT232RL when they aren't using the second port more or less (or maybe something even cooler). You could avoid software with 1 or 2 jumpers as well.

I also thought if you had a bigger CPLD you could do like a loopback kind of thing so the 2nd port is used for programming and buffered/configured though the CPLD for whatever function you wish. This looks like it will be a very useful project. Keep up the great work.

Re: UART on BBv2 MSSPE 2?

Reply #6
Actually, take a look here: http://dangerousprototypes.com/docs/Bus ... onnections

We're in luck, TXD and RXD are both on JTAG output pins (TCK, TDI). As long as TMS doesn't change (maybe a pull-up/down?), it should run fine without putting the CPLD into programming mode and having an effect.

RTS and CTS are unusable without a buffer, but the other pins are currently unconnected and could be brought to a header.
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Re: UART on BBv2 MSSPE 2?

Reply #7
That is quite lucky. I didn't look as closely as the direct of the pins. So it might be possible simply to have the serial without any isolation. Excellent.

Re: UART on BBv2 MSSPE 2?

Reply #8
Here's a post of Sjaak's that I lost in the split:

[quote author="Sjaak"]
[quote author="ian"]
JTAG seems to be a mess. I actually just use 1 to 1 female cables to connect to various devices. CPLDs and FPGAs often use a 6x1 or 5x1 header, ARM will use a 2x5, 2x8, 2x10, etc header.

http://iteadstudio.com/store/index.php? ... cts_id=246
[/quote][/quote]
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Re: UART on BBv2 MSSPE 2?

Reply #9
Just a friendly note if you're following this topic...

I split the monster thread into several small parts that should be easier to surf, but you will not get more notifications until you comment or click 'notify' on the new threads.

Bus Blaster v2 design thread http://dangerousprototypes.com/forum/in ... pic=1490.0
BBv2 CPLD design and implementation http://dangerousprototypes.com/forum/in ... pic=1659.0
urJTAG for BBv2 JTAG B http://dangerousprototypes.com/forum/in ... pic=1655.0
UART on BBv2 MSSPE2? http://dangerousprototypes.com/forum/in ... pic=1656.0
FT2232H EEPROM discussion http://dangerousprototypes.com/forum/in ... pic=1658.0
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Re: UART on BBv2 MSSPE 2?

Reply #10
[quote author="ian"]
Here's a post of Sjaak's that I lost in the split:

[quote author="Sjaak"]
[quote author="ian"]
JTAG seems to be a mess. I actually just use 1 to 1 female cables to connect to various devices. CPLDs and FPGAs often use a 6x1 or 5x1 header, ARM will use a 2x5, 2x8, 2x10, etc header.
[/quote]
[/quote][/quote]

link is lost I guess: http://iteadstudio.com/store/index.php? ... cts_id=246

Re: UART on BBv2 MSSPE 2?

Reply #11
updated, sorry about that. I couldn't figure out how to merge a single post into an existing topic.
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Re: UART on BBv2 MSSPE 2?

Reply #13
I don't see any reason we couldn't add something like that to an updated version.
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Re: UART on BBv2 MSSPE 2?

Reply #14
Great, there are a bunch of Luminary Dev boards that would support. Plus just anyone who wants the UART. Let me know if I can help in any way.