Dangerous Prototypes

Dangerous Prototypes => Bus Pirate Support => Topic started by: dangermouse on March 29, 2013, 06:21:23 pm

Title: SPI mode sample on rising clock issue
Post by: dangermouse on March 29, 2013, 06:21:23 pm
Hi,

seems the Pirate sets MOSI  (labled sdi here) 5 ns *after* SCLK.
I'd like to talk to a device with clock idle low, sample on rising edge.
Data sould be stable min. 5 ns *before* rising edge of sclk.

Am i missing something in setup?
Code: [Select]
HiZ>m
1. HiZ
2. 1-WIRE
3. UART
4. I2C
5. SPI
6. 2WIRE
7. 3WIRE
8. LCD
9. DIO
x. exit(without change)

(1)>5
Set speed:
 1. 30KHz
 2. 125KHz
 3. 250KHz
 4. 1MHz

(1)>1
Clock polarity:
 1. Idle low *default
 2. Idle high

(1)>1
Output clock edge:
 1. Idle to active
 2. Active to idle *default

(2)>1
Input sample phase:
 1. Middle *default
 2. End

(1)>1
CS:
 1. CS
 2. /CS *default

(2)>2
Select output type:
 1. Open drain (H=Hi-Z, L=GND)
 2. Normal (H=3.3V, L=GND)

(1)>2
Ready
SPI>W
Power supplies ON

SPI>[0xfe 0x00]
/CS ENABLED
WRITE: 0xFE
WRITE: 0x00
/CS DISABLED

Title: Re: SPI mode sample on rising clock issue
Post by: dangermouse on March 30, 2013, 09:18:47 am
Here i have a sample from the datasheet. This is the way the device likes to have it.
sdi mean serial data in (slave side)

Btw. what does
Input sample phase:
1. Middle *default
2. End
mean?
I thought in SPI data capture  (Data valid) can be on the rising or falling edge which means that data on the bus is allowed to change  on the adjacent edge.
Title: Re: SPI mode sample on rising clock issue
Post by: dangermouse on March 30, 2013, 04:27:09 pm
seems to be only me on this thread...

Looked into the sources and discovered that the bp uses hardware spi
flashed the bd to current version... nope.

Maybe i mixed up clock Edge?

Code: [Select]
(1)>1
Clock polarity:
 1. Idle low *default
 2. Idle high

(1)>1
Output clock edge:
 1. Idle to active
 2. Active to idle *default

(2)>2
Input sample phase:
 1. Middle *default
 2. End

(1)>1
CS:
 1. CS
 2. /CS *default

(2)>2
Select output type:
 1. Open drain (H=Hi-Z, L=GND)
 2. Normal (H=3.3V, L=GND)

(1)>2
Ready
SPI>W
POWER SUPPLIES ON
SPI>l
MSB set: MOST sig bit first
SPI>[0xFE 0x00]
/CS ENABLED
WRITE: 0xFE
WRITE: 0x00
/CS DISABLED
SPI>

This looks better, but does it match the menu readings?  *confused*
Title: Re: SPI mode sample on rising clock issue
Post by: arakis on July 15, 2013, 11:22:48 am
Hi sorry for not replaying sooner.
The problem seems to be in Microchips definition of the CKE bit Clock Edge Select bit which we call the Output clock edge.. Microchips interpretation of this is to setup when the output data changes, and not when it's ready...
So if idle to active is set, this is the point at which the data line will be changed from lats say bit7 to bi6 etc...and data is ready to be rad after this...

Do you have a sugestion on how we might rename this setting for easier understanding..