I have read the following passage:
I needed something to help me sleep so I decided to read the datasheets of the mcix and winbond...
Found something interesting in regard to disabling the write protect bit which will mean more to people with actual knowledge about programming.
The mcix's writing protect is disabled #cs goes low -> send instruction -> cs goes high
Whereas the winbond mentions #cs goes low -> shifting the 06h instruction into the rising edge of the clk -> cs goes high
Now i get most of it, expect the part
Shifting the 06h Instruction into rising edge of CLK
What does it mean? How can this be achieved?
Can anyone please help?
Does this mean that i have to run the 06h instruction in sync with the CLK line?
I think you are referring to a spi device (rom?)
basicly it says pull cs down, write the byte (0x06 in the example) and raise cs. The data is expected to be valid by the chip when the clk goes high. Mostly the datasheet has a nice diagram were this is drawn.
On wikipedia there is also an article with some timingdiagrams: http://en.wikipedia.org/wiki/Serial_Per ... erface_Bus (http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus)
the buspirate is capable of sending/receiving bytes on a SPI bus, more details here: http://dangerousprototypes.com/docs/SPI (http://dangerousprototypes.com/docs/SPI)