HI, I didn´t like to disturb this post, I´m reading with interest and becomes a question to me. In agilent and tek oscilloscopes after the 16XXX implements a type of trigger more specific and very usefull to me. I think that can be implemented from the client and translate as "normal" advance trigger sequences, but may be it´s easy to implement in demon core directly. I refer to teh triggers for the serial protocols like USART, I2C, SPI, CAN, LIN, etc (in this order of importance) that permit, for example, establish that certain channels are I2C channels and speak to the clients in term of protocol instead of terms of crude bits. That is that we can establish for example the start condition as a simple click, r/W as a check box, then put a condition for the I2C address and perhaps data and this in a simple form and the client or demon decode the sequence of triggers to execute this trigger.
It´s like an inverse decoder, but it´s really usefull and fast. I offer to help with this if you need.
My memories of the ST Std Peripheral library are that it was more painful to use than just writing code from scratch.
Almost for the last two years the original library was replace with the ARM standard for ALL ARM products CMSIS. Using this library you can compile your program in any ARM controller only changing few headers. Its a big improvement over other processors, it´s easy of implement and have standard librarys for all the devices inside the controller. You need to remember that M3 it´s a microcontroller, not a microprocessor and it´s optimized for this task.
I really did not like use of pointer indirection for everything.
Why??? It´s the key for power on several languages and it´s the must for efficient class implementation. Pointer indirection it´s fast, optimist and the compiler do the stuff for you to produce great and compact code.
At this point, use the microcontroller that you like and fill comfortable, program in the language that you prefer and without doubt you can finish in less time than if you use a new fancy controller that not like to you. I move everything to ARM because exist a lot of devices that are compatible and I can select the best price performance ratio.
Sorry, I not see the file yet, but you say that this is a sniff of a "secure flash communication", which device is it? A Secure Digital Flash Memory ? In this case you are seeing SDIO not I2c, that is, SPI or 1 bit mode or 4 bit mode.
I not only work with 5 volt, but at the moment I have not choice when work with HP probes. I like in the near future (before OLS 2.0) to work with other signal level, and in fact, 3.3 volt it´s the facto standard that I use. With the 1/3 attenuation, I have control of line from 3.3 to 5 volt (vcc to part 1.5 volt and 2.5 respectively) using an other buffer solder instead actual buffer and perhaps 2.5 volt. Using 1/2 attenuation I have the entire range, but need to measure at work the final waveform for check to excessive ringing.
Other option it´s to build a wing for work specifically with Agilent probes or something with the same characteristics and then use your improved suggested circuit or perhaps the comp circuit suggested in other posts.
Where you live? If we do the wing I can send you the PCB or even the circuit with components soldered for free. Everything open source off course and published here.
I´m using the 16XXX probe too but in 5 volt, I have an old one and now buy a new one because they are great for the cost, but it´s true that is not cheap, but isn´t so expensive if you need a good probe.
How bad it´s in the real life use a resistance of 100K instead of 49.9K? With that someone not need to make a wing, only change the buffer and the things can work (replacing the buffer off course).
For example, using the 74AVC16T245 yo can obtain the threshold for 1.8 volt if VCC it´s 0.8 volt and other input threshold varying the VCC, they work to me better that other solutions and it´s cost effective (propagation time in next paragraphs), but I follow you with this and never tray SSTL2 logic to do this. I love to test everything that seems good or interesting and you take this seriously. Do you have in mind any part to put in replace or companion of current buffer?
If you drop the voltage enough to make that work, the propagation delay becomes very large.
YES! That its VERY true, but I assume that only a small fraction of users use OLS at really high speed. For example, the part that I random select (maybe with carefully search this would be improved) at lowest VCC (0.8) has a propagation delay of 15ns that limits OLS to 60 Mhz and it´s ugly, but at 1.1 volt (2.5 volt at inputs) has 7nS of delay. I not read about buffers of Texas in last years, but someone in laboratory uses their low voltage series up to 300Mhz, I dont know which is the High input threshold. The advantage of using this translators it´s that we can direct replace the buffer in the current board with very low changes.
Can you post a schematic too? It´s more clear to ask. Thanks. I have a question, it´s not more stable to use some of the new dual supply translating buffer like the 74ALVC164245 (from NXP, although limited to 100Mhz, exist other parts to +200 Mhz)? I use these parts to scan buses with different VCC and works like a charm, every threshold was correct without need to float the signal and are really cheap. Simply change the second VCC with a jumper to the level that you like to scan and all it´s OK.
Have you measured the differences in the propagation time between the inputs with the 16XXX probe and the FPGA input?
Thanks again for your effort to have a better OLS.
I'd also prefer keeping a SPI connection, since its 50-100X faster than serial
I´m lost in translation, who ask for replace the SPI and use USART transmitting? I think that SPI it´s the only one cheap (free) alternative when we need fast and cheap serial download or control. I used PCI and PCIe and was very challenging but powerfull and involved a lot of trial and error to polish the board for high speed noise. I use USB at max speed or ethernet at 100Mbit and was more easy than PCI in most of cases but I prefer for small distances SPI. Have you ever design something with PXI?
I´m agree, I use Agilent and Tek LA for years but LA it´s not only see that happens, it´s too precision on timing and a lot of vendor improvements that I not need in OLS. But it´true that my LA cost 2000 dollars ONLY in the plugin to debug three serial protocol that I free in OLS. OLS can´t replace my LA when I need to certify a PCI or USB device, but for students and users it´s by far a price/features invincible tool. I say that OLS have a niche where I have software features only encounter in PRO LA but the lack of a robust circuitry to acquire data, very stable clocks and MEMORY. Only the memory it´s relevant for most of the users that not pretend certify a new PXI board.
I insist with the point that we need to do all that we can do to increment the OLS memory usage through software and hardware.
Arhi, ok, I not discuss with you anymore. I buy boards frequently and pay for peek and place (not in prototypes because it´s expensive for few boards) and not see something like you told us but off course I believe you without hesitation. Maybe DP need to change boards provider if doing a board precutt, slot or similar it´s prohibited and convert a common cheap design goal in an impracticable one.
I´m took one hour to reading a lot of post about RLE that claims that the user need to use 16 bit or 32 but use less than 8 channels and I´m still thinking that it´s a waste of memory. I confirm that implements something that permit use a longest RLE than the sniffed word length it´s a valuable feature to add.
Brent, I never says that buy OLS to use as FPGA development board. For that I buy a FPGA development board.
You insist in the cost of two boards and really it´s not true. I´m design boards like that and buy it in small quantities and the cost it´s the same really. Please, before continues arguing in something like that, see the next picture and say me if the board in this photograph is ONE or TWO boards.
If you insist that this are two boards and the extra CNC cutting doubles the price of final product then it´s OK, but the real world of electronics it´s VERY different that the scenario that you put in a lot of post that actually prevent discuss the benefits or cons of the modules.
If develop two board was a complete failure, WHY continues left space for a wing? Wing it´s not a module? It´s not a second board? I not understand your point of view that blame that opportunity of flex the OLS but claims for a memory expansion wing, in fact with a newr OLS expansion memory it´s not needed, then the cost is LOWER than in the situation argued with plenty of expansion wings with complicated CPLD only for do the job that the unused an unruted pins in the actual FPGA can do for free?. If put an extra chip of memory it´s costly, then left the footprint in the board and the user that need that solder it.
Exist a lot of projects that to this and permit more freedom to the user for the same cost. Peek and place one board, make one board, sell one board but if you break it you have two independent board. If you read my post, I never say that the user NOT buy the board one, I say "drop out". For a point of view from DP this is the same board with different routing.
I work for years with pro LA and OLS NEVER can replace it in a pro desk, but for student projects, debugging protocols and even debugging proprietary or not standard protocols the OLS find his place. I can buy an old very good 16XXX LA for the same money that buy an OLS but never I can add it protocol debugging to it. This is the strong feature of OLS, protocol debugging in LA cost a lot of money to implement in 30 or 40 units for students. I buy the OLS with improvement in mind and because DogsBody do a very smart job putting almost all the logic of one of the more succesfull LA that today still working and it´s enough in thousands of electronics benchs. But it´s true that not see users lamenting that advanced triggers it´s not implemented, definetively I wrong when think how important it´s each feature.
I not fear of redesign all, I´m working in projects several times complex, but my free time it´s very limited. Many heads think better than one and it´s good for us as developing community arguing features and discarding it with strong and real arguments. For this reasons I write here and not work alone in a dark laboratory with a bunch of students and order 50 copies of the prototype, I think that publish it´s better to all of us.
Thanks to all for read my bad english and sorry for disturb you with strange ideas.