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Topics - Tarloth

Open Bench Logic Sniffer / RLE

Yesterday I´m begin to read the Demon Core sources and a doubt arose. I read in posts that RLE word (identify with a 1 in the upper channel position, 7 or 15 bit length plus flag bit) stores the information of how many clocks the logic state at inputs maintain constant and when the counter exceeds the word length then put other word and count again. It´s that true? Why count again with other word and not nested words? Using nested counters OLS can wait forever and the memory used dramatically descend. That was contemplated and was impossible to implement in the FPGA or was never tried?

Another question, I read it before in the forum but now I not remember where. The parity bit it´s not used to denotes the RLE counter/data flag because exist any problem or because was simpler took the last channel instead use the parity bit?

Both questions it´s for me to optimize my attempt to alter the demon core code, Until january I can´t work seriously in the core but need to familiarize with FPGA tools in the spare time. Thanks
Open Bench Logic Sniffer / Glitch Capture
Sorry if this was discuss in previous post. I finish few minutes ago of read the forum to page 7 and read some to page 14 and I find some points that I rewrote this days because I´ve not read before the forum, SORRY.

This post it´s for ask if the DEMON CORE has implemented some kind of glitch capture and if somebody are interested on it.

Sorry if this was discussed
Client software / Android client

I not sure where post this question, but somebody plan to port OLS client to Android? Sorry for this question but would be very comfortable to use the OLS with a "cheap" tablet instead a notebook or PC. Even buying the tablet only for the OLS the total cost it´s several times lower than any other autonomous Logic Analyzer with similar specs.