Yesterday I´m begin to read the Demon Core sources and a doubt arose. I read in posts that RLE word (identify with a 1 in the upper channel position, 7 or 15 bit length plus flag bit) stores the information of how many clocks the logic state at inputs maintain constant and when the counter exceeds the word length then put other word and count again. It´s that true? Why count again with other word and not nested words? Using nested counters OLS can wait forever and the memory used dramatically descend. That was contemplated and was impossible to implement in the FPGA or was never tried?
Another question, I read it before in the forum but now I not remember where. The parity bit it´s not used to denotes the RLE counter/data flag because exist any problem or because was simpler took the last channel instead use the parity bit?
Both questions it´s for me to optimize my attempt to alter the demon core code, Until january I can´t work seriously in the core but need to familiarize with FPGA tools in the spare time. Thanks