CPLD: Complex programmable logic devices

{{Project
|manufacturing=Shipping
|status=Mature
|forum=http://dangerousprototypes.com/forum/viewforum.php?f=51
|purchase=http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html?cPath=174
|price=$15
}}

[[image:Xc9572-cpld-breakoutvib.jpg]]

Ever get stuck choosing the right logic chip combination or voltage level translator? Give up the hunt and create your own custom logic chip. CPLDs can give you the logic you need, with the pinout you want, while saving board space and board revisions.

Development boards from Dangerous Prototypes will help you build your first custom logic chip using simple schematic entry, Verilog, or VHDL.
*XC9572XL or XC2C64A CPLDs
*On-board power supply for core and pins
*Selectable 3.3volt or external supply for pins (1.8volt to 3.3volt)
*LEDs for output, push button for input
*Easy to program with the Bus Pirate
*Open source (CC-BY-SA)
'''[http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html CoolRunner-II] and [http://www.seeedstudio.com/depot/xc9572xl-cpld-development-board-p-799.html XC9572XL] versions available for $15.'''

==Downloads==
*[https://github.com/DangerousPrototypes/Downloads/blob/master/CPLD.Breakout.Package.v1.0.zip Download CPLD Breakout Package]
*[https://github.com/DangerousPrototypes/CPLD_Breakout Browse the project's GitHub]

==Hardware==
*[[Xilinx CPLDs: XC9500 vs CoolRunner-II]]
===XC9500XL===
[[image:Xc9572-cpld-breakoutvib.jpg|150px]]

The Xilinx XC9500XL family has some of the cheapest and readily available CPLDs out there. Inputs are 5volt tolerant and they can be run from a single 3.3volt supply.
*[[XC9500XL CPLD breakout board|XC9500XL CPLD development board]] hardware design
*[[XC9572XL CPLD dev-board introduction]]
*[[Xilinx XC9500XL CPLD quick start|XC9500XL CPLD quick start]]
*[[XC9572XL dev-board v1 errors]]
*[http://www.xilinx.com/support/documentation/data_sheets/ds054.pdf XC9500XL family manual]
*[http://www.xilinx.com/support/documentation/data_sheets/ds057.pdf XC9572XL device datasheet]
*[http://www.xilinx.com/support/documentation/data_sheets/ds058.pdf XC9536XL device datasheet] (smaller version of XC9572XL)

===CoolRunnerII===
[[image:xc2c64a_cpld_breakout-vib.jpg|150px]]

The CoolRunner-II family is newer than the XC9500XL, and has a few extra features like multiple IO voltage banks for voltage translation, internal pull-up resistors and pin keepers and a clock divider. Requires a 1.8volt core supply and a 1.2-3.3volt IO pin supply.
*[[CoolRunner-II CPLD breakout board|CoolRunner-II CPLD development board]] hardware design
*[[XC2C64A CPLD dev-board introduction]]
*[[Xilinx CoolRunner-II CPLD quick start|CoolRunner-II CPLD quick start]]
*[http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf CoolRunner-II family manual]
*[http://www.xilinx.com/support/documentation/data_sheets/ds311.pdf XC2C64A device datasheet]
*[http://www.xilinx.com/support/documentation/data_sheets/ds310.pdf XC2C32A device datasheet] (smaller version of XC2C64A used on Bus Blaster v2)

==CPLD development tutorials==
This tutorial shows how to use simple schematics to design the logic in a Xilinx CoolRunner-II or XC9500 CPLD.
*[http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html Free Xilinx ISE Webpack download]

Tutorial files:
*See [https://github.com/DangerousPrototypes/Downloads/blob/master/CPLDdev.package.v1.1.zip CPLDdev.package.v1.1.zip]
The Bus Pirate XSVF player and a .bat file are included with every example. Modify the COM post and click to load.
===Schematic entry===
*[[CPLD intro 1: Light a LED]]
*[[CPLD intro 2: Toggle a LED with a button]]
*[[CPLD intro 3: Inverse LED toggle]]
===Verilog===
*[[CPLD Verilog intro 1: Light a LED]]
*[[CPLD Verilog intro 2: Toggle a LED with a button]]
*[[CPLD Verilog intro 3: Inverse LED toggle]]
===VHDL===
*[[CPLD VHDL intro 1: Light a LED]]
*[[CPLD VHDL intro 2: Toggle a LED with a button]]
*[[CPLD VHDL intro 3: Inverse LED toggle]]
*[[CPLD intro 4: replacing simple logic vhdl|CPLD VHDL intro 4: Replacing simple logic]]

===Plunify===
[http://www.plunify.com Plunify] is a cloud-based compiler for <s>Xilinx</s> and Altera chips. <s>The CPLD examples are already loaded, all you have to do is sign up for a free account and copy the tutorial from the ''add IP'' tab.</s> Unfortunately it no longer supports Xilinx chips.

*[http://www.youtube.com/watch?v=WWFyVMZUMRE How-to video: use Plunify with the CPLD examples]
*[[Plunify online compiler overview]]

===ISE Webpack===
*[[Export (X)SVF from Xilinx ISE Webpack]]
*[[CPLD: simulate designs]]
*[[Enable CoolRunner-II CPLD pull-up resistors]]

==Example devices==
*[https://github.com/DangerousPrototypes/Downloads/blob/master/CPLDdev.package.v1.1.zip CPLDdev.package.v1.1.zip]
*[https://github.com/DangerousPrototypes/CPLD_Breakout/tree/master/package/Device_examples Latest in SVN]
===Schematic===
*[[CPLD example: Dual 74xx595s]]
*[[CPLD example: Dual latch]]
*[[CPLD example: FIFO]]
*[[CPLD example: Motor Phase Interlock]]
*[[CPLD example: Priority Decoder]]
*[[CPLD example: PWM Generator]]
*[[CPLD example: Addressable Latch]]
===VHDL===
*Our [[7400 series library in VHDL]]
*[http://opencores.org/project,mcpu 32 macrocell CPU] at OpenCores.org
*[[CPLD ring oscillator]] a clock source without a crystal

===Verilog===
*[[Lulu:_Yet_another_logic_analyzer|Logic analyzer example in 72 macrocells]]

==Programming==
*[[Bus_Pirate_JTAG_XSVF_player|CPLD programming with Bus Pirate, XSVF loader, and XSVF files]]
*[[CPLD programming with Bus Blaster, urJTAG, and SVF files]] (currently CoolRunner-II only)
*[[JTAG SVF to XSVF file converter]]
===Additional methods===
*[http://www.xilinx.com/itp/3_1i/pdf/docs/jtg/jtg.pdf Parallel cables with IMPACT]
*[http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf XSVF player for any microcontroller] (used in Bus Pirate XSVF player)
*[http://www.clifford.at/libxsvf/ lib(X)SVF]
*[http://rmdir.de/~michael/xilinx/ FT2232 programmers and IMPACT with alternate driver]

==Links==
===Verilog===
*[http://www.asic-world.com/verilog/synthesis.html Synthesis tutorial] (a favorite tutorial)
*[http://www.asic-world.com/tidbits/index.html Verilog concepts] (wire, reg, blocking, etc)

==Resources==
*[[Xilinx CPLD breakout development scraps]]
*[[CPLD development board manufacturing resources]]

==License==
*Hardware: CC-BY-SA
*CPLD demos projects: CC-0
[[Category: Projects ]]
[[Category:Tutorials]]
[[Category:Xilinx]]