Bus Blaster v2 manufacturing resources
From DP
Contents |
Setup
Download and install the drivers:
Download and install urJTAG:
Download the CPLD implementation:
Programming the CPLD with urJTAG
Bus Blaster v2 can program the CPLD itself using our patched version of urJTAG. Hopefully our patches will be included in an official release soon.
Patched urJTAG
We patched urJTAG to allow the Bus Blaster v2 to self-program. Follow these steps to setup:
- Download and install UrJTAG
- Copy the patched .exe file (urjtag-revXX.exe) to the install location (C:\Program Files\UrJTAG)
- Copy \bsdl and \svf to c:\, or see the notes section below.
Program
In this step we load the CPLD with the buffer logic.
First, start the patched urJTAG by running the patched exe file (urjtag-revXX.exe) and connect Bus Blaster v2 USB to a computer.
jtag> cable ft2232 interface=2 Connected to libftd2xx driver. jtag>
Select the Bus Blaster programmer.
jtag> bsdl path c:/bsdl jtag>
Copy the xc2c32a.bdsl file to a directory and tell urJTAG where to find it.
jtag> detect IR length: 8 Chain length: 1 Device Id: 00000110111000011100000010010011 (0x06E1C093) Filename: c:/bsdl/xc2c32a_vq44.bsd jtag>
Enumerate the devices.
jtag> svf c:/svf/bbv2.svf progress stop Parsing 660/663 ( 99%) Scanned device output matched expected TDO values. jtag>
Copy the .SVF file to a directory. Run the Bus Blaster v2 SVF file. Show progress, stop on errors.
For multiple units:
- Press the up arrow once to display the last svf command
- Press enter to repeat the final step
Notes
- The cable type for the self-program connection is FT2232, option interface=2 targets the CPLD
- Our patched version of urJTAG requires path names with / instead of \
- Copy the bsdl file to c:\bsdl, or change the path in the bsdl setup command
- Copy the bbv2.svf file to c:\svf, or change the path in the svf command
Test the hardware
Connections
We will chain scan the FPGA on the Logic Sniffer to verify the Bus Blaster functionality. You can use any simple FPGA, CPLD, or ARM development board for the test instead.
| Bus Blaster JTAG | Logic Sniffer JTAG |
|---|---|
| VTG | 2V5 |
| GND | GND |
| TCK | TCK |
| TDO | TDO |
| TDI | TDI |
| TMS | TMS |
- Connect the Bus Blaster to the Logic Sniffer as shown in the table
- Plug in the Bus Blaster USB
- Plug in the Logic Sniffer USB
Function test
- Start urJTAG
jtag> cable jtagkey
- Setup the Bus Blaster interface with "cable jtagkey"
jtag> detect
- Perform the chain scan with "detect"
- urJTAG detects a Xilinx device, manufacturer unknown
Errors
jtag> detect Warning: TDO seems to be stuck at 1
If the chip is not detected:
- Check the JTAG connection
- Make sure there are no other FTDI chips attached to the PC (urJTAG might attach to wrong programmer)
Old program method using Bus Blaster v1
Connections
We used urJTAG and Bus Blaster v1 to program the CPLD in Bus Blaster v2. Hopefully Bus Blaster v2 will be able to program the CPLD itself, but urJTAG doesn't yet support the secondary JTAG channel on the FT2232.
| Bus Blaster V1 JTAG | Bus Blaster v2 JP1 |
|---|---|
| VTG | 3V3 |
| GND | GND |
| TCK | TCK |
| TDO | TDO |
| TDI | TDI |
| TMS | TMS |
- Plug in the Bus Blaster v1 USB to the programming computer
- Plug in the Bus Blaster v2 USB to a DIFFERENT computer (so the driver is not confused)
- Connect the Bus Blaster v1 JTAG header to the Bus Blaster v2 JP1 as shown in the table
Program
In this step we load the CPLD with the buffer logic.
jtag> cable jtagkey
Select the Bus Blaster programmer.
jtag> bsdl path c:\bsdl
Copy the xc2c32a.bdsl file to a directory and tell urJTAG where to find it.
jtag> detect
Enumerate the devices.
jtag> svf c:\svf\bbv2.svf progress stop
Copy the .SVF file to a directory. Run the Bus Blaster v2 SVF file. Show progress, stop on errors.
For multiple units, just repeat the final step.