Bus Blaster v2 manufacturing resources

From DP

Contents 1 Setup 2 Programming the CPLD with urJTAG 2.1 Program 2.1.1 Notes 3 Test the hardware 3.1 Connections 3.2 Function test 3.2.1 Errors 4 Old program method using Bus Blaster v1 4.1 Connections 4.2 Program

Setup

Download and install the drivers:

• Windows, Linux, MAC

Download and install urJTAG:

• UrJTAG

Download the CPLD implementation:

• Bus Blaster v2 JTAGKEY CPLD implementation

Programming the CPLD with urJTAG

Bus Blaster v2 can program the CPLD itself using our patched version of urJTAG. Hopefully our patches will be included in an official release soon.

1. Plug in the Bus Blaster v2 USB to a computer

Program

In this step we load the CPLD with the buffer logic.

jtag> cable ft2232 interface=2
Connected to libftd2xx driver.
jtag>

Select the Bus Blaster programmer.

jtag> bsdl path c:/bsdl
jtag>

Copy the xc2c32a.bdsl file to a directory and tell urJTAG where to find it.

jtag> detect
IR length: 8
Chain length: 1
Device Id: 00000110111000011100000010010011 (0x06E1C093)
Filename:     c:/bsdl/xc2c32a_vq44.bsd
jtag>

Enumerate the devices.

jtag> svf c:/svf/bbv2.svf progress stop
Parsing    660/663 ( 99%)
Scanned device output matched expected TDO values.
jtag>

Copy the .SVF file to a directory. Run the Bus Blaster v2 SVF file. Show progress, stop on errors.

For multiple units, just repeat the final step.

Notes

• The cable type for the self-program connection is FT2232, option interface=2 targets the CPLD
• Our patched version of urJTAG requires path names with '/' instead of '\'
• Copy the bsdl file to c:\bsdl, or change the path in the bsdl setup command
• Copy the bbv2.svf file to c:\svf, or change the patch in the svf command

Test the hardware

Connections

We will chain scan the FPGA on the Logic Sniffer to verify the Bus Blaster functionality. You can use any simple FPGA, CPLD, or ARM development board for the test instead.

test connections

Bus Blaster JTAG	Logic Sniffer JTAG
VTG	2V5
GND	GND
TCK	TCK
TDO	TDO
TDI	TDI
TMS	TMS

1. Connect the Bus Blaster to the Logic Sniffer as shown in the table
2. Plug in the Bus Blaster USB
3. Plug in the Logic Sniffer USB

Function test

• Start urJTAG

jtag> cable jtagkey

• Setup the Bus Blaster interface with "cable jtagkey"

jtag> detect

• Perform the chain scan with "detect"
• urJTAG detects a Xilinx device, manufacturer unknown

Errors

jtag> detect
Warning: TDO seems to be stuck at 1

If the chip is not detected:

• Check the JTAG connection
• Make sure there are no other FTDI chips attached to the PC (urJTAG might attach to wrong programmer)

Old program method using Bus Blaster v1

Connections

We used urJTAG and Bus Blaster v1 to program the CPLD in Bus Blaster v2. Hopefully Bus Blaster v2 will be able to program the CPLD itself, but urJTAG doesn't yet support the secondary JTAG channel on the FT2232.

programming connections

Bus Blaster V1 JTAG	Bus Blaster v2 JP1
VTG	3V3
GND	GND
TCK	TCK
TDO	TDO
TDI	TDI
TMS	TMS

1. Plug in the Bus Blaster v1 USB to the programming computer
2. Plug in the Bus Blaster v2 USB to a DIFFERENT computer (so the driver is not confused)
3. Connect the Bus Blaster v1 JTAG header to the Bus Blaster v2 JP1 as shown in the table

Program

In this step we load the CPLD with the buffer logic.

jtag> cable jtagkey

Select the Bus Blaster programmer.

jtag> bsdl path c:\bsdl

Copy the xc2c32a.bdsl file to a directory and tell urJTAG where to find it.

jtag> detect

Enumerate the devices.

jtag> svf c:\svf\bbv2.svf progress stop

Copy the .SVF file to a directory. Run the Bus Blaster v2 SVF file. Show progress, stop on errors.

For multiple units, just repeat the final step.