Logic Shrimp design overview

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Project Summary
Name: Logic Shrimp design overview
Buy it: Get one for $34.90 at Seeed Studio
Price: $34.90
Status: Test production
Manufacturing: Testing
Forum: Logic Shrimp design overview Forum

The Logic Shrimp is a medium speed, low cost logic analyzer with 256K samples and 20MHz top speed:

  • 4 channels @ 256K samples per channel
  • 5volt tolerant inputs
  • 20/12/6/3/2/1MHz capture rates, and lower
  • Simple edge change triggers on all channels, adjustable pre/post trigger samples
  • SUMP protocol compatible
  • USB interface, USB firmware upgradable
  • Open source (CC-BY-SA)

Available for $34.90 at Seeed Studio.

Read about the design below.




A few years ago Microchip started pushing a new serial RAM chip, the 23K256. This chip has 256Kbits (32Kbytes) of storage in a small 8pin package and runs at up to 20MHz. When we demoed this chip with the Bus Pirate, it seemed ideal for a single-channel logic analyzer probe.

Fast forward a bit: IPenguin linked to the SCANALOGIC 2 in the forum, an AVR-based logic analyzer and frequency generator that uses four of these nifty SRAMs. Newly inspired by this design, we set out to build an open source, SUMP-compatible logic analyzer using the 23K256.

The Logic Shrimp design is diagrammed above. Four 23K256 SRAMs capture up to 256K samples on each channel. The SRAMs run at 3.3volts, but the Logic Shrimp inputs are 5volt tolerant thanks to a 74LVC573 buffer. A PIC 18F24J50 configures the SRAMs and provides a capture clock source: etiher from the pulse-width modulator, or from a 20MHz oscillator though a one-bit buffer.



Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.


Logic-shrimp v1-microcontro .jpg

A PIC 18F24J50 (IC5), the 3.3volt version of the famous 18F2550 USB family, is the microcontroller for this project. The PIC handles the USB connection, the SUMP protocol interface, and configures the SRAMs to capture logic signals.

This chip is an extended life product and should be available for many years in the future.

  • C1 and C4 (0.1uF) are small capacitors on the supply pins for decoupling
  • C11 is a 10uF tantalum capacitor for the 2.5volt core regular inside the PIC
  • The PIC is programmed though the ICSP header, resistor R4 holds the programming/reset pin high for normal operation
  • 20MHz oscillator Q2 is the clock source for the PIC
  • ACT is an indicator LED
  • The entire circuit is powered by 3.3volt regulator VR1, with supply capacitors C12 (10uF) and C10 (1uF)



Four 23K256 serial SRAMs (IC1-IC4) store the logic analyzer samples, each has a 0.1uF capacitor for decoupling (C5-C8).

Sch-Logic-Shrimp-v1a-SRAMs .png

The clock pins are gently pulled down by R5 (1M ohm) to prevent false samples when changing between clock sources.

Each SRAM input pin is connected to both the 5volt tolerant buffer and a PIC pin. The PIC configures the SRAM, then opens the buffer during capture.

Each SRAM output is connected to a PIC pin, and brought to the CH OUTPUT header. With software and firmware support, the output header could replay logic or be used as a signal generator.


Sch-Logic-Shrimp-v1a-buffer .png

Signals enter the logic analyzer through a cheap and common 74xx573 transparent latch (IC7), we've used this on previous logic analyzers. The input buffer does two things:

  1. Enables/disables the signal inputs so the PIC can setup the SRAMs for capture and playback
  2. The SRAM and PIC pins only work to 3.3volts, the buffer is 5volt tolerant

During logic capture the buffer is transparent: input from the buffer connects to the SRAM data input pins. During setup and playback, the buffer is disabled so the PIC can take control of the SRAMs.


We chose the LVC version of the buffer:

  • VIH high-level 2volts minimum
  • VIL low-level 0.8volts maximum
  • VI input 5.5volts maximum

Astute observers will notice we used an LVT buffer because we had it on hand. The manufactured version ships with a LVC buffer.

The buffer is 8bits wide, but we only need 4. Unused inputs are grounded to reduce noise in the other channels.

Clock system


A 20MHz oscillator (Q2) provides a clock source for the PIC.

The SRAMs store a snapshot of the data on the serial input pin at each pulse of the clock pin. The clock signal can come from two sources:

  1. 12MHz and less, from the PIC pulse-width modulator
  2. 20MHz from the oscillator. Enabled through a 74LVC1G125 1bit buffer (IC6). Pull-up resistor R3 holds the buffer off when the PIC is reset


The PIC configures the SRAMs to record, and then enables the clock source. The SRAMs run in a loop, always recording the state of the serial data in pin.

The active clock source drives an address counter in the PIC that tracks the current storage address in the SRAMs. We have to track the SRAM address on the PIC so we know where our samples are located inside the SRAM when the capture ends. There is no way to retrieve the current address from the SRAM directly.

When trigger fires, a second sample counter starts. This counter runs down until the configured post-trigger sample size is reached, then the PIC disables the clock source.

The PIC address counter mirrors the internal SRAM counters when sampling ends. Its value is used to calculate the address where we need to start dumping samples.

There is an external tap for the clock signal, but it is not possible to use an external clock.
An external clock would interfere with the PIC when the SRAMs are setup and dumped.

Geeky tidbit: the PIC counters are only 16bits, which can only track 64K of the 256K total SRAMs. We use a /4 prescaler on both counters to line everything up. This is a great solution because the SUMP protocol also sends the sample counts divided by four.



We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.



Click for a full size placement image.

Part Quantity Value Package
C1-C9 8 0.1uF C0603
C10 1 1uF C0603
C11,C12 2 10uF SMC_A
IC1,IC2,IC3,IC4 4 23K256-I/SN SOIC8
IC5 1 PIC18F24J50-I/SS SSOP28
IC6 1 74LVC1G125 SOT-23-5
IC7 1 74LVC573 SO20W
INPUT 1 0.1” pin header 1X05-S
Q2 1 20Mhz 3.3volt Oscillator OSCILLATOR_7X5_SMD
R1,R2,R4 3 2K R0603
R3 1 10K R0603
R5 1 100K R0603
VR1 1 3.3volt VREG LDO 100mA+ SOT23-5

The latest sources and distributors are in the master partlist. See something missing? Please let us know.


The Logic Shrimp supports a sub-set of the SUMP logic analyzer protocol.

The firmware is written in C and compiled with the free Microchip C18 compiler. You can download the latest files from our Google Code project page.

We used the Microchip USB stack to run the 18F24J50 as a virtual serial port. Microchip's code is open but not redistributable. If you want to compile the source, download the stack from Microchip, then drag the source code into the install directory. See the detailed instructions in the PIC compiler how-to.

.inf installation

The virtual serial port (CDC) is an open standard, it should work on any modern operating system.

You don't need a driver, but you will need an .inf file to tell Windows how to use the device. A suitable .inf is included in the project archive.


Easy firmware updates over USB are possible using the Diolan USB HID bootloader. Multi-platform update utilities are included in the project archive.

Taking it further

V1 of the firmware is extremely simple, there's lots of room for new features.

  • The triggers leave a lot to be desired
  • Frequency and signal generator features can be added by recording to the SRAMs and replaying

In a v2 hardware update we'd like to replace both buffer chips with a CPLD. The CPLD could also support advanced triggering not possible with the PIC.

We'll post the most recent firmware updates on our blog. You can also join the discussion in the forum.

Get one!


You can get a Logic Shrimp for $34.90 only at Seeed Studio.

Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!



  • Hardware: CC-BY-SA
  • Firmware: CC-BY-SA
  • Bootloader: GPL