CPLD: simulate designs

From DP

After a successful 'build' a simulation of the design is possible.

Start simulation

Change the view from 'implementation' to 'Simulation' and doubleclick 'Simulate Behavioral Modal'. We used the tutorial 4 files for the simulation.

Setup clock signal

And a 'Force clock' to both inputssignals.

• Right-click on 'Value' and select 'Force clock'
• We add a squarewave with a period of 100ms to in1 and a squarewave with a period of 200ms to in2.

Run simulation

Select the 'run-all' option.

By zooming in a simular simulation is visible.