Bus Blaster v1 design

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Bus Blaster v1 is an experimental high-speed JTAG debugger design, it is no longer available. Please see Bus Blaster v2.

  • Fully buffered interface works with 3.3volt to 1.2volt targets
  • Based on FT2232H with high-speed USB 2.0
  • Compatible with 'jtagkey' programmer type in OpenOCD, urJTAG, and more
  • Open source (CC-BY-SA)

Bus Blaster v1 is now available to early adopters at a discount. Each unit is tested with a real JTAG target before it ships.

Read about the design below.



Project Summary
Name: Bus Blaster v1 design
Buy it: Get one for $35, including worldwide shipping at Seeed Studio
Price: $35, including worldwide shipping
Status: Test production
Manufacturing: Discontinued
Forum: Bus Blaster v1 design Forum

The Bus Blaster is used to program and debug devices with a JTAG interface like ARM processors, CPLDs, flash memory, and more. It has a JTAGkey-compatible buffer interface that is supported by most popular open source JTAG utilities.

This project was developed in a public forum, and progress was documented on a wiki.


Bus Blaster-v1-cct.png

Click for a full size schematic image. Schematic and PCB were designed with the freeware version of Cadsoft Eagle, download the latest project files from our Google Code project page.



The FT2232H is a powerful USB to serial communication chip. It has an MPSSE feature that provides a simple USB to JTAG converter (and UART, I2C, or SPI). Most DIY JTAG debuggers use this chip, as do many commercial models.

Bus Blaster v1 uses the 'H' version of the chip, the latest 3.3volt revision that supports JTAG adaptive clocking. The circuit is based on a reference design from the FT2232H datasheet.

We chose not to populate the optional EEPROM on Bus Blaster v1 in order to stay within our price goals. It is not required, and without it the FT2232 uses default settings.

Buffered interface


The buffer translates voltage levels between the FT2232H (3.3volts) and a JTAG device (1.2volts-3.3volts). The buffer is the primary difference between the Bus Blaster and a plain FT2232H development board.

The buffer is powered by the target, 1.2volts to 3.3volts only
You must connect the target power supply to the JTAG VTG pin


The four main JTAG IO pins (TDI, TDO, TCK, TMS) are at fixed locations on the FT2232, but the other control pins vary among programmers. We wanted the Bus Blaster to work 'out of the box', so we used a buffer compatible with the Amontec JTAGkey style interface.

The jtagkey interface is common among DIY programmers, and it's already supported in most open source JTAG utilities. We reverse engineered the connections from the OpenOCD source code and verified them against the Openmoko debug board v3 schematics.

The buffer is NOT 5volt compatible.


Outputs (Bus Blaster->target)
pin FT2232 pin description notes
TDIADBUS1 JTAG data in to target
TCK ADBUS0 JTAG clock in to target
TMS ADBUS3 JTAG state machine update
TRSTACBUS0 Reset output
TSRSTACBUS1 Bi-directional reset pin
DGBRQACBUS4Debug request Reserved for future use

A SN74AVC4T245 level shifter (IC4, IC5) converts 3.3volt FT2232 input to 1.2volt-3.3volt output for the target circuit.


Inputs (target->Bus Blaster)
pin FT2232 pindescription notes
TDOADBUS2JTAG data out from target
TSRST ADBUS6Bi-directional reset pin Connected to TSRST output
RTCKADBUS7 System return clock For adaptive clocking
DGBACKACBUS5Debug acknowledge Reserved for future use
VTGADBUS5Voltage target detectSimple transistor with pullup resistor, inverts signal

Signals from the target to the FT2232 are level shifted by a 74AVC2T45 voltage translator (IC6, IC7, IC8). It is hard-wired to input from the target.



We used the freeware version of Cadsoft Eagle to make the schematic and PCB. Download the latest designs and firmware from the project Google Code page.



Click for a full size placement image.

Parts Quantity Value Package
C1-C7, C13-C21, C25 17 100nF C805
C8 1 3.3uF SMC_A
C9, C10 2 27pF C805
C11, C12, C22 3 4.7uF SMC_A
IC1 1 FT2232H LQFP64
IC3 1 LD1117-3.3 SOT223
IC4, IC5 2 SN74AVC4T245 TSSOP16
JTAG 1 02x10 shrouded header, male 0.1” PAK100/2500-20
L1, L2 2 800mA+ ferrite bead FB805
R1 1 12K R805
R2, R9 2 1K R805
R3, R4, R5, R7 4 10K R805
R6 1 2.2K R805
R8 1 100k R805
R10, R11 2 470R R805
T1 1 NPN transistor, 100mA+ SOT23-BEC
X1 1 12MHz crystal, small package 4X6

The latest sources and distributors are in the master partlist. See something missing? Please let us know.

Taking it further

We're already hard at work on Bus Blaster v2. The updated design replaces the discrete buffer chips with a CPLD. V2 will be cheaper and more flexible.

Get one!

Bus Blaster v1 is now available to early adopters at a discount. Each unit is tested with a real JTAG target before it ships.

You can get a Bus Blaster v1 for $35, including worldwide shipping.

Your purchases at Seeed Studio keep the open source project coming, we sincerely appreciate your support!



Hardware license: CC-BY-SA