Bus Blaster buffer logic

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Contents

Overview

Bus Blaster v2+ is buffered by a reprogrammable CPLD instead of discrete logic chips. New buffer logic can be loaded so the Bus Blaster appears like many common JTAG programmer types. These are the currently available buffer clones:

Buffer logic for Bus Blaster v2/v3/v4 ARE NOT COMPATIBLE!

Buffers for Bus Blaster v3

joefitz published some working buffers for Bus Blaster v3 on the forums, along with useful advices on getting BBv3 to work.

jtagkey

The JTAGkey is probably the most commonly cloned buffer configuration among FT2232-based JTAG programmers. It is compatible with OpenOCD, urJTAG, and more.

Schematic

Bbv2-jtagkey-cpld-v11.png

Issues

Crossworks: Cannot set debug register errors in OSX, Linux. Known to effect all JTAGKEY programmers. Works fine with "conservative" parameters:

  • Adaptive clocking: No
  • JTAG Clock Divider: 2
  • nSRST/nTRST Open Drain: Yes

OpenOCD 0.5.0 and PandaBoard: PandaBoard debug with BusBlaster V2 with Windows fails. Do not use OpenOCD 0.5.0 from here it does not work correctly. A build of OpenOCD 0.5.0 under cygwin works fine. As seemingly does the 0.7.0 binary from the link above.

KT-link

The KT-link is the first FT2232 JTAG debugger with support for new SWD and SWV JTAG protocols. The libswd project is adding support for SWD to OpenOCD and urJTAG, and the KT-link will be the first supported programmer. Bus Blaster v2+ supports SWD only! Bus Blaster v2+ does not support SWV because one required pin is used to program the CPLD

Schematic

Bbv2-ktlink-v1.png

Issues

  • Crossworks: this buffer may fail on Liunux

PicoTAP

PicoTAP is a the hardware for the goJTAG open source software with a friendly GUI. A PicoTAP-compatible buffer is available for the Bus Blaster v2+.

The PicoTAP dongle is based on the FT2232 and has simple connections:

  • ADBUS0(16)->TCK
  • ADBUS1(17)->TDO
  • ADBUS2(18)<-TDI
  • ADBUS3(19)->TMS
  • ADBUS4(20)->nTRST

This buffer is written in Verilog. Latest source in Git.

Thanks roglio for the suggestion.

Programming

Bus Blaster v2+ can program the CPLD itself using urJTAG.

Our patches are included in the current urJTAG SVN source. Unfortunately there is no release that includes it yet. We have a patched .exe for Windows, or you can compile it yourself.

Download and install the drivers:

Download and install urJTAG:

Download the CPLD buffer bitstream (and patched urJTAG):

Patched urJTAG

The download includes a patched urJTAG.exe to allow the Bus Blaster v2+ to self-program. Follow these steps to setup:

  1. Download and install UrJTAG
  2. Copy the patched .exe file (urjtag-revXX.exe) to the install location (C:\Program Files\UrJTAG)
  3. Copy \bsdl and \svf to c:\, or see the notes section below.

Program

Patched-urjtag-full-program-bbv2-v1.png

In this step we load the CPLD with the buffer logic.

First, start the patched urJTAG by running the patched exe file (urjtag-revXX.exe) and connect Bus Blaster v2+ USB to a computer. 

jtag> cable ft2232 interface=1
Connected to libftd2xx driver.
jtag>

Select the Bus Blaster programmer.

  • The cable command connects to the FT2232 chip
  • ft2232 programmer type
  • interface 1 is the CPLD JTAG connection 
jtag> bsdl path c:/bsdl
jtag>

Copy the xc2c32a.bdsl file to a directory and tell urJTAG where to find it.

  • bsdl path sets a directory to search for BDSL files.
  • BSDL is a file format that describes the CPLD chip on Bus Blaster v2+. It tells urJTAG how to program the CPLD 
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00000110111000011100000010010011 (0x06E1C093)
Filename:     c:/bsdl/xc2c32a_vq44.bsd
jtag>

Enumerate the devices.

  • The detect command searches for attached JTAG devices using a JTAG chain scan
  • The device ID is displayed
  • urJTAG searches its database and the BSDL path for a device that matches the ID 
jtag> svf c:/svf/bbv2.svf progress stop
Parsing    660/663 ( 99%)
Scanned device output matched expected TDO values.
jtag>

Copy the .SVF file to a directory. Run the Bus Blaster v2+ SVF file.

  • svf command plays the .SVF file and programs the CPLD
  • progress displays the percent complete
  • stop ends programming if there is an error

Notes

  • The cable type for the self-program connection is FT2232, option interface=1 targets the CPLD
  • Our patched version of urJTAG requires path names with / instead of \
  • Copy the bsdl file to c:\bsdl, or change the location in the bsdl path command
  • Copy the bbv2.svf file to c:\svf, or change the path in the svf command

Buffer pin connections

FT2232 to CPLD connections

Buffer pin connections
FT2232 name FT2232 pin CPLD v2 CPLD v3CPLD v4
ADBUS0/TXD/TCK/SK 16161260
ADBUS1/RXD/TDI/DO 17141358
ADBUS2/RTS#/TDO/DI18131456
ADBUS3/CTS#/TMS/CS19121655
ADBUS4/DTR#/GPIOL02183953
ADBUS5/DSR#/GPIOL12264052
ADBUS6/DCD#/GPIOL22354150
ADBUS7/RI#/GPIOL32434249
ACBUS0/TXDEN/GPIOH02624343
ACBUS1/GPIOH12714442
ACBUS2/GPIOH22844241
ACBUS3/RXLED#/GPIOH32943340
ACBUS4/TXLED#/GPIOH43042539
ACBUS5/GPIOH53241127
ACBUS6/GPIOH63340637
ACBUS7/GPIOH73439836
BDBUS0/TXD/TCK/SK38111117
BDBUS1/RXD/TDI/DO399916
BDBUS2/xxx/TDO/DI40242415
BDBUS3/CTS#/TMS/CS41101014
BDBUS4/DTR#/GPIOL043xx35
BDBUS5/DSR#/GPIOL144xx34
BDBUS6/DCD#/GPIOL245xx33
BDBUS7/RI#/GPIOL346xx32
BCBUS0/GPIOH148xx30
BCBUS1/GPIOH252xx29
BCBUS253xx28
BCBUS3/RXLED#/GPIOH354xx24
BCBUS4/TXLED#/GPIOH455xx23
BCBUS5/GPIOH557xx22
BCBUS6/GPIOH658xx19
BCBUS7/GPIOH759xx18

v4 schematic

Busblaster-v41a-buffer-a.png

Click for larger sizes.

v3 schematic

Busblaster-v3-buffer-a.png

Click for larger sizes.

v2 schematic

Busblaster-v2-buffer-a.png

Click for larger sizes.

CPLD to JTAG header connections

JTAG header connections
JTAG header CPLD
TRST 38
TDI 37
TMS 36
TCK 34
RTCK 33
TDO 32
TSRST 31
DBGRQ 30
DBGACK 29
IO9 28
IO10 27
V_TARGET 26
BD2 24
IO11 23
IO12 22
IO13 21
IO14 20
IO15 19
Retrieved from "http://dangerousprototypes.com/docs/Bus_Blaster_buffer_logic"