23K256 32K serial RAM

From DP

Jump to: navigation , search



The 23K256 is a serial SRAM chip. It works pretty much like an EEPROM, but it's a lot faster and doesn't retain data without power.

Pin Diagram

       _____ _____
/CS __|1    U    8|__ VCC
      |           |
 SO __|2         7|__ /HOLD
      |           |
 NC __|3         6|__ SCK
      |           |
VSS __|4         5|__ SI


Bus Pirate Direction 23K256 Description
MOSI SI Master Out, Slave In
MISO SO Master In, Slave Out
CLK SCK Clock signal
CS /CS Chip Select (Active LOW)
AUX (or +3.3V)/HOLD Pauses SRAM, HIGH for normal operation (Active LOW)
+3.3VVCC Connect to external power (see Note)
GND VSS Signal Ground

Note: Do not use Bus Pirate power, rather connect to an external 3.3V power. Read the following limitation.

Bus Pirate setup

Connect the Bus Pirate to the chip as shown in the table.

In the below section, <<<some text is not the actual terminal output. These text are just used for illustration.

HiZ>m<<<mode command
1. HiZ
5. SPI
(1)>5<<<SPI mode
Select output type:
1. Open drain (H=Hi-Z, L=GND)
2. Normal (H=3.3V, L=GND)
(1)>2<<<normal pinout

Configure the Bus Pirate for SPI mode. Chose all the default settings except output type. Choose normal pin outputs.

SPI>W<<<enable power supplies
Power supplies ON

If the chip is powered by the Bus Pirate enable the power supplies (W).

SPI>A<<<AUX pin to 1

The HOLD pin pauses the SRAM when active(low), set the auxiliary pin to ground (a) for HOLD or Vcc (A) for normal operation.


23K256 commands
Command Description
0x01 write to configuration register
0x05 read from configuration register
0x02write data (requires 2 address bytes, n data bytes)
0x03read data (requires 2 address bytes, read n data bytes)

We'll cover these four commands. The commands are sent after taking the CS pin to ground ([), transactions end by returning CS high (]). Transactions have this basic format:

[ command write/read ]

Configure the chip

Configuration register (0x01)
7 6543210
access modexxxxxHOLD disable

The first thing we need to do is setup the chip for access. The configuration register is shown in the table above. It's accessed by writing 0x01 to the SRAM, then sending new configuration settings.

The 23K256 has 32K bytes of RAM arranged into 1024 32byte pages. The RAM can be accessed in several modes, but the most interesting for most uses is sequential access mode. Sequential mode allows reads and writes anywhere in the storage space.

SPI>[0x01 0b01000001]
WRITE: 0x01<<<config update command
WRITE: 0x41<<<Config register value

Writing 01 to bits 7 and 6 of the configuration register set the access mode.

The HOLD pin functions can be disabled by writing 1 to bit 0 of the configuration register.

SPI>[5 r]
WRITE: 0x05
READ: 0x41

Read back and verify the configuration with command 0x05.

Write data

SPI>[0x02 0 0 5 6 7 8 9 10 11 12 13]
WRITE: 0x02<<<write command
WRITE: 0x00<<<address H
WRITE: 0x00<<<address L
WRITE: 0x05<<<data to write
WRITE: 0x06
WRITE: 0x07
WRITE: 0x08
WRITE: 0x09

Store data in the chip with the write command (0x02). Next send a two byte address that tells the chip where to store the data. Finally, send as much data as you like.

If you send more than 32K it will wrap around and overwrite the earliest data.

Read data

SPI>[0x03 0 0 r:9]
WRITE: 0x03<<<read command
WRITE: 0x00<<<address H
WRITE: 0x00<<<address L
READ: 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D <<<data

Access data in the chip with command 0x05, followed by a two byte address. We read from the beginning of the chip where we wrote our values earlier.

The Bus Pirate read command (r) uses a repeat (:9) to return multiple bytes.