Coolrunner GCK - maximum frequency?

[tonyennis]

I need to supply a clock to my DP Coolrunner board. The frequency doesn't have to be very high in the scheme of things. However, I want to be sure I choose a clock that isn't too fast.

The data sheet says "Maximum external frequency(3)" is 108MHz. I am interpreting this to be the clock I would supply. Does anyone have any insight into whether this interpretation is correct?

[hlipka]

This actually depends on what you are doing inside of the CPLD. The given frequency is the maximum when you don't to anything timing-relevant (basically any DFF or gate will consume some amount of time in the timing paths, and will reduce the frequency). Xilinx ISE will do a timing analysis when it is synthesizing your design, and will calculate the maximum frequency for your inputs. But typically you can expect something around 75% o the maximum frequency as long as you don' do any crazy stuff.

[tonyennis]

Ah, I knew some report existed, I had never looked at it. I see the following in a few places:

Code: Select all

                  Minimum Internal Clock Period(Tcyc): 39.7ns
                     Maximum Internal Clock Speed: 25.1Mhz
                            (Limited by Cycle Time)

                     Minimum External Clock Period: 39.7ns
             Maximum External Clock Speed (before divider): 25.1Mhz
                            (Limited by Cycle Time)

So I'm looking at about 25MHz tops, then? The 25.1MHz is the smallest of the "Maximum External Clock Speed" values.

[hlipka]

Yes, in that case the frequency is limited to 25MHz. If this is not enough, you can look at the details of the timing analysis to see which path limits this. (Actually the maximum frequency should be listed right at the top).

I think 25MHz is rather slow. In my last design I had 2 24bit-counters (chained from 8bit-ones) with gated clock signals, and some additional logic on the outputs, and I got about 70MHz out of a 10ns XC9572XL. So you must have some heavy logic in there...

[tonyennis]

Not really sure why it's so low. The only time the clock is used is in one module, for quadrature decoding. The problem being solved is fairly linear, so the encoded signal is decoded then trickles through a module that performs a 'ROM' lookup and another that's a 15 bit adder/subtracter.

The clock is used to detect state transitions in a quadrature encoded signal. The clock's freq has to be at least double that of the encoded signal. The encoded signal has a modest frequency. It turns out I need a clock of about 400KHz. So the 25MHz limit is wholly acceptable. I'll have a wide range of affordable oscillators from which to choose.