So, here's a trick that occurred to me the other day that might come in handy for a logic analyzer (for instance).
Suppose you have a parallel RAM or ROM module that you want to stream data into and out of at high speed. You need to be able to jump to any arbitrary address, but your normal mode of operation is streaming.
It'd be nice to be able to address the module using a shift register, since that requires far fewer GPIOs. But now you have to clock addresses into the shift register serially for every address you want to read or write - for an n bit memory module, that's n clocks before you can do the read or write operation.
However, it's possible to stream data in and out with only a single clock per address. Here's how: Instead of addressing the memory sequentially, use an LFSR
. External LFSRs have two very useful properties here. First, each state can be generated by shifting the previous state one bit to the left (something our shift register already does) and computing the next bit with a straightforward XOR operation. Second, it iterates through every n bit combination before returning to its initial address. Thus, we can stream data by repeatedly evaluating the next bit of the LFSR, but we can still jump to an arbitrary address by shifting an entire address in at once.
I think this could be pretty useful for building a logic analyzer: you can hook the probes up to the data lines of the memory module via a tristate buffer, then iterate through the RAM at high speed to take samples. To output the samples, you do the same thing, but use parallel reads or another shift register to read the data out.
Of course, doing streaming analysis with a buffer isn't really practical unless you use a dual port RAM chip or add additional mux/demux hardware to interleave reads and writes.
What do you think? Useful trick?