What header should be exposed through an OLS case?

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What header should be exposed through an OLS case?

Postby Max » Mon Nov 19, 2012 5:13 pm

I intend to design a case/enclosure for the OLS (Open Bench Logic Sniffer) that can be made using 3D printing. When the design is done, I will make the STL design files freely available for everyone to download from Thingiverse.com.

The OLS is still new to me, so I have some questions about what parts of the OLS should be user-accessible through the enclosure for 2 different scenarios.

All possible headers and buttons are included in both selection lists for completeness, and to help ensure I do not make any mistakes designing the OLS enclosure.

I thank everyone in advance for their help and participation.

Scenario 1
Which header(s) and button(s) should be accessible through the enclosure to use the OLS as a logic analyzer; without ever upgrading or modifying the firmware on the OBLS?:
  • JP1 - Mini USB
  • J2P - ICSP
  • JP3 - Program Enable
  • JP4 - Extern Header (EXT_CLOCK_OUT and EXT_TRIGGER_OUT)
  • JP5 - ROMISP
  • JP6 - JTAG
  • JP7 - I/O Header
  • JP8 - I/O Header
  • JP9 - Extern Header (FPGA_AUX3 and EXT_CLOCK_IN)
  • JP? - UART
  • WING1G$1 - Wing Header
  • S1 - Reset Button
  • S2 - Update Button

Scenario 2
Which header(s) and button(s) are used to install, upgrade, or modify the firmware on the OLS?:
  • JP1 - Mini USB
  • J2P - ICSP
  • JP3 - Program Enable
  • JP4 - Extern Header (EXT_CLOCK_OUT and EXT_TRIGGER_OUT)
  • JP5 - ROMISP
  • JP6 - JTAG
  • JP7 - I/O Header
  • JP8 - I/O Header
  • JP9 - Extern Header (FPGA_AUX3 and EXT_CLOCK_IN)
  • JP? - UART
  • WING1G$1 - Wing Header
  • S1 - Reset Button
  • S2 - Update Button

I did read the all the OLS documentation.
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Re: What header should be exposed through an OLS case?

Postby tkg » Mon Jun 17, 2013 7:45 pm

Hi Max,

I think this page http://dangerousprototypes.com/2010/02/ ... nalyzer-2/ has a good overview of the intended functionality for each header.

Regarding Scenario 1, the very minimal version for the headers would be JP1(usb to connect to a pc), JP7 and JP8 as 8 or 16 inputs. If you require 32 inputs then you also need to expose the wing header. The wing header is a bit more difficult as some wings can go to the side. Please note that the wing also includes the two groups of gnd-2v5-3v3-5v headers (for powering the chips from a wing) not only the main row of pins.

If you plan to use an external clock or chain multiple OLS boards then also JP9. If you would like to chain multiple OLSs then also JP4 (don't know if this is currently supported).

That would be all.

Regarding the rest of the headers,

The reset button ... resets the pic uC and the update one is currently used to put the PIC in the update mode for the FPGA stream (it might be used in combination with the reset button).

The JP2 is used to program/debug the PIC (say if there is no bootloader present) or to start the PIC bootloader in the PIC firmware update mode.

JP3 can be used to put the FPGA in reset so that it does not attempt to use the flash memory chip and it can be used together with JP5 to program the flash memory directly from an SPI compatible device.

JP6 - can be used to program/debug the FPGA.

JP? (UART) could be used to communicate with the PIC using a serial protocol at say 3.3v levels (but not directly RS232 voltage levels!)

Regards,
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