LED D1 and D2 source current from the CPLD. Generally, designers sink current from CPLDs and FPGAs - the chip connects the LED to ground instead of power - because many parts can sink 20mA but only source a few. On this chip, however, the maximum current is a paltry 4mA for both source and sink. The LEDs have 2K resistors (R2,R3) that keep the current at an acceptable 2mA.
I intend to sink LEDs using the CPLD. Does this mean any pin can sink 4mA, or the total of all sinkage can be 4mA, or do I misunderstand completely?