SUMP compatible Arduino based logic analyzer.

A cheap logic analyzer. Get one for $50, including worldwide shipping. A collaboration between the Gadget Factory and Dangerous Prototypes.

SUMP compatible Arduino based logic analyzer.

Postby gillham » Tue Mar 08, 2011 3:13 am

Hello everyone.

I work in Silicon Valley in the networking field and electronics are just a hobby. One that I am not that great at yet, but nevertheless a fun one.

I recently got an Open Bench Logic Sniffer from the Gadget Factory and found it to be a very handy device, even though I haven't had any direct experience with commercial logic analyzers.

Initially I had looked around for an Arduino based logic analyzer since I had a handy Arduino board and an interest in making a simple signal / function generator, but needing a way to very the timing. Sadly I didn't find any ready to work projects and what little I found was Windows only and I have a Mac laptop.
Eventually I stumbled across the SUMP project, discussions of the Bus Pirate and of course the OLS. At that point I realized the Bus Pirate I had already would work with SUMP and set about upgrading it. Reading through the SUMP docs the protocol looked simple enough that I thought "Why not try implementing this on the Arduino?" and set about it. After getting my code to respond appropriately and kind of working with the client I went about trying to get some accuracy. That is when I ordered an OLS of my own.

Ultimately I was able to get some fairly precise sampling on the Arduino by watching a debug pin with the OLS and eventually I had a really basic working SUMP compatible logic analyzer!

I call it the "Arduino Generic Logic Analyzer" or AGLA. The code is available under a BSD license here: http://github.com/gillham/logic_analyzer and I also posted about it over here: http://arduino.cc/forum/index.php/topic,52881.0.html

I asked Jawi for some help on the client adding a few tweaks to make it easier to use an Arduino. Things like a configurable delay after opening the serial port to allow the Arduino to auto-reset and become ready again. Also a toggle for the DTR pin which I found was pretty necessary under Linux. I've created a device profile for the AGLA with Jawi's client and once I have it all working I'm hoping he'll add it to the distribution if people find it useful.

I've tried to keep the code simple, mostly because I'm not that great of a programmer, but also so it is easier to follow and somewhat consistent with the ease of use goals of the Arduino project. I'm able to record 1024 samples at 1MHz with decent accuracy. (this "accuracy" comment from an inexperienced logic analyzer person remember) Basic parallel triggers seem to work ok and right now I have no plans to add more complex triggering since the Arduino is pretty limited hardware and barely has the cycles for what it is doing now.

Anyway, it might seem odd to use a good logic analyzer to make a cheap one, but I guess to some degree that was how the OLS came about, and maybe the BP SUMP mode. Now to push the feature down into even less capable hardware we have the AGLA. ;)

The BP initially and then the OLS were invaluable for my work and getting accurate timing. I've used my OLS to look at an SPI connection from my Arduino to a graphical LCD and frankly the OLS can't be beat for the price. That being said, the AGLA has some usefulness as well, I think, and I'm hoping it will serve to whet people's appetites for using logic analyzers and positively contribute to the SUMP & OLS community.

-Andrew
gillham
Newbie
Newbie
 
Posts: 2
Joined: Tue Mar 08, 2011 2:31 am

Re: SUMP compatible Arduino based logic analyzer.

Postby ian » Tue Mar 08, 2011 3:24 am

Thanks for sharing Andrew,

Nice work. I have also enjoyed making SUMP compatible devices on many different platforms in the past. It's a nice little protocol that's fairly easy to use. Fantastic that there is an Arduino port now, even more people will be exposed to Jawi's great work on the client :)

For the trigger - do you use AND or OR type? I always use simple OR (any masked pin with the correct value triggers), but it seems like you have it tied together (all masked pins must match direction setting).
User avatar
ian
Crew
Crew
 
Posts: 10578
Joined: Mon Jul 06, 2009 6:14 am

Re: SUMP compatible Arduino based logic analyzer.

Postby ian » Tue Mar 08, 2011 3:25 am

Sorry about the aggressive spam filter. I fixed the links in your post.
User avatar
ian
Crew
Crew
 
Posts: 10578
Joined: Mon Jul 06, 2009 6:14 am

Re: SUMP compatible Arduino based logic analyzer.

Postby gillham » Tue Mar 08, 2011 3:49 am

It is an AND right now as I was just mirroring how my OLS was behaving and it seemed the way to go. Thanks for the welcome and feedback. Oh and fixing my links. I'll check back tomorrow (ok, later today) as I need some sleep.
gillham
Newbie
Newbie
 
Posts: 2
Joined: Tue Mar 08, 2011 2:31 am

Re: SUMP compatible Arduino based logic analyzer.

Postby Richard Sharpe » Thu Mar 10, 2011 10:40 am

What did you think of the SUMP protocol?

I found the big endian/little endian confusion in the '1ALS' response to the ID request interesting.

Also, there is an off-by-one in the logic sniffer client I was working with. Jan agrees and will fix it. When he requests samples, the value set up for the SET READ & DELAY COUNT is actually ((samples requested)/4) - 1.

I was struggling with all this over last weekend while trying to make progress on my FPGA project for my class. I am doing a thing called CheapScope, a tool for doing logic analyser for inclusion on Xilinx FPGAs.

I will make the Verilog available, such as it is, but it uses PicoBlaze because the class introduced PicoBlaze. The verilog currently has some cruft in it because I needed to use the LCD on my Genesys dev board for debugging, and I have not actually hooked up the logic sniffing verilog yet; I was just sending back synthetic data to make sure that I could communicate with the client.
Richard Sharpe
Newbie
Newbie
 
Posts: 10
Joined: Sat Dec 26, 2009 1:03 am

Re: SUMP compatible Arduino based logic analyzer.

Postby ian » Thu Mar 10, 2011 11:51 am

the value set up for the SET READ & DELAY COUNT is actually ((samples requested)/4) - 1.


When I first implemented it, I just sniffed the outgoing commands to the serial port and reversed it that way. I do recall some discrepancies with the docs, and I use the above formula in the IR Toy, Bus Pirate, and other stuff that implements SUMP.
User avatar
ian
Crew
Crew
 
Posts: 10578
Joined: Mon Jul 06, 2009 6:14 am

Re: SUMP compatible Arduino based logic analyzer.

Postby Richard Sharpe » Thu Mar 10, 2011 12:08 pm

ian wrote:
the value set up for the SET READ & DELAY COUNT is actually ((samples requested)/4) - 1.


When I first implemented it, I just sniffed the outgoing commands to the serial port and reversed it that way. I do recall some discrepancies with the docs, and I use the above formula in the IR Toy, Bus Pirate, and other stuff that implements SUMP.


Sigh, I made a mistake. The value I was seeing was ((samples requested)/4) - 2 ...

Ie, if I asked for 512 samples, the numbers I got were 7E, at least from the download of the client I did last weekend.

If it were doing as I first stated I would expect 7F.
Richard Sharpe
Newbie
Newbie
 
Posts: 10
Joined: Sat Dec 26, 2009 1:03 am

Re: SUMP compatible Arduino based logic analyzer.

Postby ian » Thu Mar 10, 2011 12:20 pm

Here's the source to the Bus Pirate SUMP engine, It's public domain, so steal as you like.

http://code.google.com/p/the-bus-pirate ... rce/SUMP.c
User avatar
ian
Crew
Crew
 
Posts: 10578
Joined: Mon Jul 06, 2009 6:14 am

Re: SUMP compatible Arduino based logic analyzer.

Postby Richard Sharpe » Thu Mar 10, 2011 12:35 pm

ian wrote:Here's the source to the Bus Pirate SUMP engine, It's public domain, so steal as you like.

http://code.google.com/p/the-bus-pirate ... rce/SUMP.c


Thanks. It will help with getting things correct.

I am working with PicoBlaze, so I have to work in assembler :-(

Probably eventually should move that stuff into the FPGA, but first I would like to move to Xilinx primitives.
Richard Sharpe
Newbie
Newbie
 
Posts: 10
Joined: Sat Dec 26, 2009 1:03 am

Re: SUMP compatible Arduino based logic analyzer.

Postby kinsa » Thu Mar 10, 2011 6:07 pm

Richard Sharpe wrote:the value set up for the SET READ & DELAY COUNT is actually ((samples requested)/4) - 1.

This is actually a bug on the client side. If the SET READ or DELAY COUNT is less than 4, what gets transmitted is 0xFFFF. The VHDL logic only works with unsigned numbers, so a -1 request translates to 0xFFFF counts.

This problem is evident if you set the "Before/After ratio" to "100/0".

UPDATE:

This has already been fixed on the latest OLS release.
kinsa
Newbie
Newbie
 
Posts: 15
Joined: Thu Feb 24, 2011 2:42 am

Re: SUMP compatible Arduino based logic analyzer.

Postby xinumike » Wed Mar 16, 2011 7:15 am

I am having issues with the endianness too I believe.

I send up 'SLA1' and '1ALS' and various other unbelievable combinations and the client software quickly goes to a no device connected mode.

I am trying to get a PIC32 based device talking.

Any ideas?

Thanks,
Mike
xinumike
Newbie
Newbie
 
Posts: 1
Joined: Tue Mar 15, 2011 7:45 pm

Re: SUMP compatible Arduino based logic analyzer.

Postby ian » Wed Mar 16, 2011 7:25 am

"1ALS" should be correct. There is not really ever another reply from the client except for sending data.
User avatar
ian
Crew
Crew
 
Posts: 10578
Joined: Mon Jul 06, 2009 6:14 am

Re: SUMP compatible Arduino based logic analyzer.

Postby flubberlab » Sun Mar 20, 2011 3:22 am

ian wrote:For the trigger - do you use AND or OR type? I always use simple OR (any masked pin with the correct value triggers), but it seems like you have it tied together (all masked pins must match direction setting).


I share Richard's OLS Basic Parallel trigger AND-stage design/usage interpretation. I figured to get ORed level triggering, one would assign each ORed channel/pattern to a unique "sum" term.

My take on the trigger was this (no Delay or Start Capture shown, and '+'/'*' = OR/AND):
TRIGGER = STAGE1 + STAGE2 + STAGE3 + STAGE4, where
STAGEn = (input * MASKn) == (input * VALUEn)

(all stages checked each sample period)

It took a little thinking to do edge triggering, e.g input0 rising in this case:
MASK1 = MASK2 = 1
ARM1 = 0 (immediate)
VALUE1 = 0
START1 = 0
ARM2 = 1
VALUE2 = 1
START2 = 1
flubberlab
Jr. Member
Jr. Member
 
Posts: 50
Joined: Sun Jan 30, 2011 5:44 am
Location: Seattle, WA

Re: SUMP compatible Arduino based logic analyzer.

Postby ian » Sun Mar 20, 2011 5:37 am

I agree that AND is the "proper" way, but I have always been lazy when implementing it on tiny devices :) I set a change interrupt on the masked pins (with edge select in some PIC models), and start sampling on first interrupt.

Code: Select all
assign trigger=(((pins[7:0] ^ trigger_value[7:0]) & trigger_mask[7:0])==0);


Here's the trigger used in the SUMP VHDL core from the Logic Sniffer. I recently used it in a CPLD demo project. I think it would probably work well in a microcontroller too.
User avatar
ian
Crew
Crew
 
Posts: 10578
Joined: Mon Jul 06, 2009 6:14 am


Return to Open Bench Logic Sniffer