[Entry]A CPLD based 8x8 game-of-life

[Entry]A CPLD based 8x8 game-of-life

Postby udif » Wed Oct 31, 2012 10:05 pm

Sorry for the terse post, but my time is running out (deadline in a few hours).

My entry to the 7400 competition is a CPLD based 8x8 game of life.
Yes, I saw there was another 8x8 game of life posted in the competition forum, but when I saw it in the forum it was too late for me to change mine, and anyhow the designs are entirely different.
Image
Please be sure to check the REAMDME.txt file in the attached ZIP with all the details.

Pictures:
https://picasaweb.google.com/udi.finkel ... _Suo6my7wE

Video:
http://youtu.be/2Ykv4kL7CUk

Here is a short quote from the README file:
Algorithm:
A 64 bit cyclic shift register is shifted to the right on every cycle. cell 0 is always the center cell, and a 6 bit row/column counter tracks the logical position of this cell. The neighbouring cells are collected, taking into account the playing field edges (we dont wrap around), and the resulting nine bits are summed. The sum output and current cell value are used to calculate the new cell value. The output value is then pushed into a shift register so that the new value won't affect the remaining calculation for this generation. The shift register replaces the old value at the point where it can no longer affect current gen calculations.
New starting patters can be entered by a joystick that moves up/down/left/right and a center button that toggles the current cell value.
The next gen is calculated by pressing a switch.

Implementation:
The project was coded in Verilog, using many small modules. The reason for that was that I wanted to be able to easily fit it into multiple XC9572XL boards I had. The naive approach would have been to put the large data shift register in one device, and the rest of the logic in a 2nd device, but this turned out to be impossible due to lack of I/O's in the other device. I ended up parametrically splitting the data array between the two devices so I can easily balance a few macorcells here or there in each device, if the need arises. I also made sure the design fits in an XC2C128 device I had.
The design itself is fully parameterized, and changing the X,Y parameter at the top level will infer the correct logic for any size chosen. Two extra redundant parameters, LOG2X and LOG2Y were added because Icarus Verilog does not support constant functions yet (which would have enabled us to calculate the LOG2 value within each block).
A test bench was prepared that generated a test pattern, and watched the LED output signals to reconstruct the display on each generation. The output was then displayed.

A third device was added for side tasks such as debouncing the input switches, dividing the original clock, and leaving room for a future capacitive touch input.


The following diagram helps understanding the core logic that calculates the game:
Image
All the project files are attached in the zip file.
The only thing missing is a true schematics, but I ran out of time. The schematics can be easily inferred from the 3 CPLD UCF I/O pin lists (all pins with identical names should be connected together).
clk_in driven by a 23MHz oscillator
row<n> drives a ULN2803A, which sinks the low side of a 8x8 LED array
col<n> drives a 74LS245 , which drives the high side of a 8x8 LED array through 1.1K resistors.
key_XXX are hooked up to a mini 40way digital thumb joystick.
One I/O button on the CPLD breakout boards is used for reset
Another I/O button on the cap_touch CPLD is used as key_next (advance game state).
Attachments
life.zip
Project files (Verilog, pin assignments, README, 'C' simulation model)
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udif
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