Trigger sync limitations

The Logic Pirate is a medium speed, low-cost logic analyzer with a USB interface. It can capture up to 256K samples at 20MHz (80MHz with overclock), and is compatible with SUMP logic analyzer client. Get one for $30 at Seeed Studio. Logic Shrimp support available here.

Trigger sync limitations

Postby octal » Tue Apr 12, 2011 12:01 am

the design of Logic Shrimp reproduces the Scanalogic2 (with a PIC instead of AVR of course), but do you think it's correct at 20Mhz?
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Re: is Logic Shrimp's desing correct?

Postby ian » Tue Apr 12, 2011 1:04 am

but do you think it's correct at 20Mhz?


What do you mean?

The PIC 18FxxJ50 PICs can take a 20MHz clock. The internal oscillator is only rated for a 16MHz crystal, but we are using an external oscillator (not a crystal).
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Re: is Logic Shrimp's desing correct?

Postby octal » Tue Apr 12, 2011 2:43 am

The pb is not there Ian,
I understand how this thing is working. I have also a scanalogic and it has a pb with 20Mhz.
both LA use a tristate gate to switch on the 20MHz osci (since even the AVR is not able to generate the 20Mhz from its pins and do something else like checking trigger conditions or buffer size at same time).

The problem is that, at any trigger condition, if you start sampling by activating the tristate gate, you'll be in one of two conditions:
1- The oscillator is generating a falling edge: this is OK since the SPI-RAMs sample data on falling edge
2- The oscillator is generating a raizing edge: You'll not sample data until next falling edge, so you'll miss 1/2T data, this means you'll sample data at 1/2T later than the trigger condition, and at 20Mhz this is somewhat a lot.
This is not a problem when you sample simple "low" protocols like SPI (<6Mhz) or RS232 (any rate), but this can be a problem when you go for 10Mhz for signals not having a specific protocol.

I think that because of kind of problems FPGA/CPLD are mandatory when going to high speed sampling.

I personally used my OWLS (bought from Seeed) to debug and confirm this problem whith my own Scanalogic2 (altought this later is really a great deal when working on most protocols and for any hobbist circuit).
I may acquire a Logic Shrimp and contribute to developements if I have enought free time.
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Re: is Logic Shrimp's desing correct?

Postby ian » Tue Apr 12, 2011 2:59 am

Ah, I see. I don't think I did the same thing in the Shrimp.

In the shrimp -
1. The SRAM capture is ALWAYs running in a loop. You can adjust 0-100% before/after trigger
2. The PIC has two timers, one is always tracking the SRAM address, the other is a down-counter for the samples
3. At trigger condition, the PIC starts the down-counter
4. When down-counter is 0, PIC stops capture by raising CS

See also the diagram and explanation of the clock system:
http://dangerousprototypes.com/docs/Log ... ock_system

A 20MHz oscillator (Q2) provides a clock source for the PIC.

The SRAMs store a snapshot of the data on the serial input pin at each pulse of the clock pin. The clock signal can come from two sources:

1. 12MHz and less, from the PIC pulse-width modulator
2. 20MHz from the oscillator. Enabled through a 74LVC1G125 1bit buffer (IC6). Pull-up resistor R3 holds the buffer off when the PIC is reset

Logicshrimpwithclock.png

The PIC configures the SRAMs to record, and then enables the clock source. The SRAMs run in a loop, always recording the state of the serial data in pin.

The active clock source drives an address counter in the PIC that tracks the current storage address in the SRAMs. We have to track the SRAM address on the PIC so we know where our samples are located inside the SRAM when the capture ends. There is no way to retrieve the current address from the SRAM directly.

When trigger fires, a second sample counter starts. This counter runs down until the configured post-trigger sample size is reached, then the PIC disables the clock source.

The PIC address counter mirrors the internal SRAM counters when sampling ends. Its value is used to calculate the address where we need to start dumping samples.

Geeky tidbit: the PIC counters are only 16bits, which can only track 64K of the 256K total SRAMs. We use a /4 prescaler on both counters to line everything up. This is a great solution because the SUMP protocol also sends the sample counts divided by four.


Finally, I do agree about CPLD assist on triggers. I have a v2 here on my desk that uses a CPLD to replace both buffer chips and to get 3-level triggering using the standard SUMP triggers. It is assembled and waiting for testing, but we only have a diagram on the wiki:
http://dangerousprototypes.com/docs/Log ... rk_product
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Re: is Logic Shrimp's desing correct?

Postby ian » Tue Apr 12, 2011 3:03 am

I also notice the diagram shows stop to the clock source - I simplified it to avoid confusion, I'm sorry if it is confusing instead :) The sampling is actually halted by raising CS at the end of a byte.
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Re: is Logic Shrimp's desing correct?

Postby octal » Tue Apr 12, 2011 3:07 am

Ah ... I see.
I just read the doc on the wiki, sorry for my confusion.
I'll buy one today and give it a try! (hope seeed will be quick enought)
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Re: is Logic Shrimp's desing correct?

Postby octal » Tue Apr 12, 2011 1:59 pm

Hi Ian,
from your previous post, I don't think your circular buffer technique solves the problem I discussed.
Correct me if I'm wrong.
The RAMs are continuously sampling input data, but you agree that RAMs sample only on falling edges of their clock signal.
If you check your algo (pointed in previous post), at step #3

3. At trigger condition, the PIC starts the down-counter
4. When down-counter is 0, PIC stops capture by raising CS

the pb is if #3 arrises when the clock edge is a raising edge on RAMs, even if the PIC starts the down-counter at time T0 (when trigger condition arises), the external events will not be sampled until next falling edge of clock (on RAMs) at time T0+1/2T. This means, there is no absolute garantee that sampling will happen at the same time the trigger condition happen.
The pb is that PIC does only lock sampling with CS pin, it does not lock the clock generator, I mean when PIC release the CS (to let RAMs sample input), there is absolutely no garantee that Clock on RAMs will strat by a falling edge.
On FPGA/CPLD this is handled by synchronizing the adr counter with the clock with the external event. This is absolutely impossible if you don't master the clock generator (the edge by whitch it will start), and this is the pb with Scanalogic2 and with LogicShrimp (if I understand).
I agree that this is really an extremely low pb, but it can happen (50% probability).

Is my reasoning ok or am I wrong?

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Re: is Logic Shrimp's desing correct?

Postby ian » Tue Apr 12, 2011 2:34 pm

the pb is if #3 arrises when the clock edge is a raising edge on RAMs, even if the PIC starts the down-counter at time T0 (when trigger condition arises), the external events will not be sampled until next falling edge of clock (on RAMs) at time T0+1/2T. This means, there is no absolute garantee that sampling will happen at the same time the trigger condition happen.


The down counter doesn't start until the next falling edge (PIC timer and SRAMS on the same clock). I guess I understand what you mean though, it might not be exactly when the clock is falling and if the change is short it might trigger a pin interrupt but change before the SRAM falling edge. Also, not knowing where you are in a byte can lead to an additional 8 clock ticks of uncertainty.

Wouldn't anything in that range be impossible to capture with the SRAMs though (assuming already 20MHz)?

The pb is that PIC does only lock sampling with CS pin, it does not lock the clock generator, I mean when PIC release the CS (to let RAMs sample input), there is absolutely no garantee that Clock on RAMs will strat by a falling edge.


I think I now understand what you mean, but I don't see it as a big problem. The goal is low-cost and medium speed LA. For more demanding work there is other equipment like the Open Bench Logic Sniffer with full features.
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Re: is Logic Shrimp's desing correct?

Postby octal » Tue Apr 12, 2011 2:45 pm

ian wrote:
The pb is that PIC does only lock sampling with CS pin, it does not lock the clock generator, I mean when PIC release the CS (to let RAMs sample input), there is absolutely no garantee that Clock on RAMs will strat by a falling edge.


I think I now understand what you mean, but I don't see it as a big problem. The goal is low-cost and medium speed LA. For more demanding work there is other equipment like the Open Bench Logic Sniffer with full features.


Hi Ian,
I understand that the capture is fully synchronized with the countdown timer. I meant only about the triggering of the RAMs clock on a "falling edge" exactly at trigger condition ;)

and YES this is my conclusion, at 20MHz it's already a very great tool and it already does most of what users need (especially if they sample signals at less than 10Mhz which covers 90% of most users in this categ).
Actually (as I said) I'm using a lot (for low speeds) Scanalogic and I will replace it with LogicShrimp because of two things: Scanalogic is extremely slow when transferring data to PC (especially if you sample 256Kb of data), and because I prefer to have full control on the firmware of my dev tools (it's your faults guys here at DP ;) ).
Keep us with these cool tools, and really "hat off" for this design, I never tought to the circular buffer idea ;)

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Re: is Logic Shrimp's desing correct?

Postby arhi » Tue Apr 12, 2011 8:57 pm

ian wrote:Finally, I do agree about CPLD assist on triggers. I have a v2 here on my desk that uses a CPLD to replace both buffer chips and to get 3-level triggering using the standard SUMP triggers.


Will this v2 maybe have bit more ram? 4 channels are mostly ok, 20MHz is mostly ok but more RAM is really often required (especially as there's no compression here - the sampling is done by the SRAM modules)...
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Re: is Logic Shrimp's desing correct?

Postby octal » Wed Apr 13, 2011 1:16 am

RAM size is problematic by design Arhi,
using SPI RAMs let you avoid having to manage ram address counters and all needed circuitery, and makes reading data easy by clocking RAMs again.
The main pb with RAMs size is that the biggest SPI RAMs available on market (and that does 20Mhz) are from Microchip and are 256KB!!!

Also I think (Arhi) that having too much RAM is useless. Most of the time 20 to 30 Kb is really enough in 80% of cases. The most important is to have a very good way to express triggers on complex and cascaded conditions, this way, you can really record only the data that are really usefull for you!
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Re: is Logic Shrimp's desing correct?

Postby bhunting » Wed Apr 13, 2011 8:27 am

In terms of data depth I agree that less is more. In fact 256k bits is bordering on too much to be useful.

Being able to trigger properly (complex triggers) and then a little pre and a little post data is what I have found to be most useful. Wading through megabits of trace is seldom productive, in fact in 30 years of doing this stuff I personally have never found more than a few k bits around a trigger to be useful.

I am curious, for those who want deep trace memory, what is your application? Serial data stream analysis? What else? Seriously, who walks through megabits of multi channel deep trace? Do you just grab a huge trace and then use a post processing program to search for events or triggers?
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Re: is Logic Shrimp's desing correct?

Postby arhi » Wed Apr 13, 2011 11:12 am

It really depends on what you use the LA for .. if you are debugging your own system then 4x256kbits is waaaaaaaay more then you need in 99% cases ... but if you are decoding proprietary protocol, trust me, more ram you have, easier it gets. Some sample LA I made with some static parallel ram + counter works for me fairly well and adding more ram there is "piece of cake" but I used a counter + ram on a "board" to achieve modularity so I have no triggering at all apart for the external trigger source ... wanted to make v2 with cpld but finished the original work I needed with obls ... that does show that complex triggers + compression can solve the problem but since I don't see shrimp having compression "ever" then I asked for more ram :( ... had no idea there are no larger serial rams then 256kbit that can go 20MHz :(
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