Switching over to the CPLD for glue between the SID and ESP has worked out really well. It's been a lot of fun learning more about logic, somewhat frustrating but mostly fun :)
I figure I shdould now recap how the project will work:
1. Python 6502 implementation runs the SID program and extracts the SID register values for each "frame" of the song, stores them in a FIFO. This code is pretty much complete (thanks greatly to the RealSID project by A.T. Brask https://github.com/atbrask/RealSIDShield
2. ESP receives ~100 frames (2seconds @ 50Hz) of music saves them into another FIFO, a ticker timer is set up for 50Hz which sends the frame data (registers) to the CPLD. I've got some work to do on the TCP code here and sending over to the CPLD but it should be pretty simple.
3. The CPLD clocks the SID, and works as an I/O expander putting the necessary address and data on the SID bus. I need to finalize the SPI slave and then write the glue for the SID (to assert addr and data when the shift register is full).
4. SID plays music (hopefully)
5. LM386 amplifies it
6. ??? profit ???
I've implemented a simple clock divider and a 200 bit shift register that is fed all 25 SID registers for each update from the ESP. Since the ESP SPI is done in hardware it works up to 80MHz! This is waaaaay better than the measly KHz that I I2C was giving me before with the MCP chip.
I wrote a testbench for my shift register to make sure everything is working correctly. Here it is shifting in alternating 0x00 then 0xFF for 25 bytes:
As you can see the MOSI line is just set to invert every byte so I can make sure things are working properly. In the terminal of my test bench I've also set up some debug output so I can follow the register filling up with bits:
I've chosen to do it this way so I can just shift in all 25 one-byte registers at once into one big buffer, then pass them over to another module that will handle writing the value to the bus for the SID. Right now the timing will be handled by the ESP, and that will be fine for 50 and 60 Hz songs but eventually I will build a buffer in the CPLD and have it handle all the timing because it will be much more reliable.
Finally on the ESP8266 side, here is a screenshot from my logic analyzer of the ESP sending out 25 bytes of data on the SPI bus (slowed down to a measly 4Mhz as to not overwhelm the poor Saleae):
It's all coming together! Soon I will hear bleeps and bloops!
And yes, for those interested, the next step is designing a PCB and slapping this all onto one nice PCB that you can just plug in to your stereo and stream to from anywhere.