MSP430 Launchpad Logic Analyzer

A place to document your own projects.

Re: MSP430 Launchpad Logic Analyzer

Postby jawi » Fri Nov 23, 2012 3:14 am

While the idea of adjusting the division constant is easy to implement and indeed is completely backward compatible, it also can introduce subtle bugs in read/delay ratio calculation.

I'm more inclined towards introducing new commands for setting the read/delay count. By splitting out the read/delay counts into two separate commands, we could use the full 32-bit range for both values. IMO, this makes the protocol a bit easier to understand/debug. Perhaps we should create a new thread on the OBLS forum about this (SUMPv2), as more people are currently trying to use the SUMP protocol beyond its current limitations...
User avatar
jawi
Developer
Developer
 
Posts: 571
Joined: Thu May 27, 2010 2:54 am
Location: The Netherlands

Re: MSP430 Launchpad Logic Analyzer

Postby Markus Gritsch » Mon Nov 26, 2012 3:46 am

@oPossum: Is there any purpose in connecting pin 11 of the latch to the SPI clock instead of permanently connecting it to Vcc?
User avatar
Markus Gritsch
Sr. Member
Sr. Member
 
Posts: 271
Joined: Tue Feb 09, 2010 6:54 am

Re: MSP430 Launchpad Logic Analyzer

Postby Markus Gritsch » Thu Nov 29, 2012 8:52 am

Hi,

I am currently in the process of designing a variant of the Logic Shrimp v2b. This one has 8 channels, uses a PIC32, and fits onto a 3cm x 3cm board. Here is a first rendering:

TinyLogic.png

I made some performance tests with the CDC example on a PIC32 clocked at 80 MHz, and they showed that the 256 kSamples can be sent to the PC in about 0.5 seconds. Promising.

I also plan to overclock the serial RAM chips to achieve more than 20 MSamples/s. Has anyone tried this already?

Cheers,
Markus
User avatar
Markus Gritsch
Sr. Member
Sr. Member
 
Posts: 271
Joined: Tue Feb 09, 2010 6:54 am

Previous

Return to Project logs